IPMP/IPMC Gpio Control, LPC Bus Control | Emerson ATCA-9305 manual

Management Processor CPLD: MPC8548 PLD Register

IPMP/IPMC GPIO Control

This register provides access (if required) to signals between the KSL CPLD and the IPMP, as well as to signals between the KSL CPLD and the IPMC. The lower two bits can request request the power down of a Cavium core from the sticky reset register.

Bits:	Function:	Description:
7	IPMC2KSL4	Input only

6	IPMC2KSL3

5	IPMC2KSL2

4	IPMC2KSL1

3	IPMP2KSL4	Output only

2	IPMP2KSL3	Output only

1	IPMP2KSL2	Power-down signal for Cavium 2 (output)
		Assert high to shut down the core. The sticky Cavium reset also
		causes this to be asserted.

0	IPMP2KSL1	Power-down signal for Cavium 1 (output)
		Assert high to shut down the core. The sticky Cavium reset also
		causes this to be asserted.

LPC Bus Control

This is the control register for the 4-bit LPC bus. It allows for communication with the IPMC controller from the management CPU.

Bits:	Function:	Description:
7	LPCIE	LPC Interrupt Enable

6	LPCS	LPC State (internal use only)

5

4

3

2	LPCIOE	LPC I/O Error

1	SYNCE	SYNC Error

0	SYNCT	SYNC Time-out

LPC Data

This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC controller from the management CPU. This register provides the data to be sent or received, depending upon the commands given in the control register.

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ATCA-9305 User’s Manual

10009109-01

ATCA-9305 specifications

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In conclusion, the Emerson ATCA-9305 is a powerful and versatile chassis that stands out due to its high-density configuration, advanced thermal management, diverse interconnect technology support, robust security features, and comprehensive management capabilities. Its design is tailored for the evolving needs of telecommunications and data center environments, making it a valuable asset for any organization looking to enhance its infrastructure.

Emerson ATCA-9305 user manual IPMP/IPMC Gpio Control, LPC Bus Control, LPC Data

Models: ATCA-9305