Emerson ATCA-9305 Cavium 1 Cmul Clock Divisor Control, Cavium 2 Cmul Clock Divisor Control

Management Processor CPLD: MPC8548 PLD Register

Register 5-20:RTM Control (0x68)

Bits:	Function:	Description:
7	0
6	0
5	0
4	RTMP	RTM is Present
3	RTMID3	RTM Identification bits 3:0
2	RTMID2	0000	= Test RTM (factory only)
1	RTMID1	1000	= 20GbE I/O RTM
		1100	= 18GbE and 2x10GbE I/O RTM
0	RTMID0
		1010	= Storage RTM

Cavium 1 C_MUL Clock Divisor Control

Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.

Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).

!

Register 5-21:Cavium 1 C_MULL Clock Divisor Control (0x70)

Bits:	Function:	Description:
7	CAVF	Cavium Frequency resistor set bit (read-only)
		00	600
6
		01	750
		10	800
		11	reserved
5	CMULOE	C_MUL Output Enable
4	P1CMUL4	These bits drive directly to the Cavium 1. The core clock speed
		is the number multiplied by 50 MHz. For example, the 800 MHz
3	P1CMUL3
		core is set to 16(0x10).
2	P1CMUL2
1	P1CMUL1
0	P1CMUL0

Cavium 2 C_MUL Clock Divisor Control

Use the C_MUL2 register to reduce the speed of the Cavium CN5860 processor 2 core.

Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).

!

10009109-01 ATCA-9305 User’s Manual

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