Management Complex: Memory
10009109-01 ATCA-9305 User’s Manual 4-7

MEMORY

The memory devices in the management complex consist of:
• 1 GB DDR2 SDRAM
• 512 KB socketed flash
• 8 MB soldered NOR flash (two redundant banks of 4 MB each)
• 1 GB soldered NAND flash
• 512 Mb or 64 MB soldered NOR flash

SDRAM

This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory mod-
ule (SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus oper-
ating at 200 MHz. The MPC8548 detects all double-bit errors, multi-bit errors within a
nibble and corrects all single-bit errors.
The 128M X 72 DDR2 SDRAM is a high-density, un-buffered SO-CDIMM. This module con-
sists of nine 128x8-bit with eight banks DDR2 SDRAMs, a zero delay phase-lock loop (PLL)
clock, and a 2 KB serial presence detect (SPD) EEPROM. The SDRAM starts at physical
address 0000,000016.

Flash

There are several flash devices on the local bus interfacing the CPLD and MPC8548 proces-
sor. The four soldered flash banks are labeled 1 through 4:
• Banks 1 and 2 are the MPC8548 U-boot banks (see “4M x 16”). These boot banks are
used in the boot redirection scheme, see “Boot Device Redirection (BDR).”
• Banks 3 and 4 are physically one device, but appear in the software as two banks of 32
MB (see “64 MB x 16”). These are for general purpose storage.
512 KB x 8 (optional)
The 512 KB of 32-pin PLCC socketed flash starts at physical address FC80,000016 and is used
for Engineering code. The StrataFlash (P33) features high-performance fast asynchronous
access times, low power, and flexible security options.
4M x 16
The two 4 MB soldered flash devices are used for MPC8548 boot code. This redundant bank
configuration allows booting from either bank in case of corruption in one bank. See “Boot
Device Redirection (BDR)” on page7-41. The SST NOR flash devices are organized as 4Mx8