Emerson ATCA-9305 Cavium Processor Complex

10009109-01 ATCA-9305 User’s Manual 3-1

Section 3

Cavium Processor Complex

The ATCA-9305 provides two Cavium processor complexes. The major devices on each

complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,

RLDRAM®, an I2C EEPROM, socketed ROM, Flash, and the PCI bus interface.

Figure 3-1: Cavium Processor Complex Bl ock Diagram

CAVIUM CN5860 PROCESSOR

The main features of the CN5860 include:

Table 3-1: CN5860 Features

Feature: Description:

Processor Core Up to 16 cnMIPS™ cores

Core Speed

Network Services Processor (NSP)

up to 800 MHz, processing up to 30 million packets per second

System Packet Interface Two SPI-4.2 ports

L2 Cache 2 MB, eight-way set associative

DRAM 144-bit DDR2 DRAM interface

RLDRAM 18-bit RLDRAM, low-latency memory direct access

PCI 64-bit, PCI 2.3 compatible

Console

(ENG use only)

PCI Bus

I2C

EEPROM

COP/

JTAG

BCM56802

XAUI 10 Gb

Switch

5 XAUI

XAUI 13

XAUI 14

PCI Bus

IDSEL13

6 XAUI

Console

(ENG use only)

Cavium

Octeon

CN5860

Processor 1

SPI-1

PCI

Bus

IDSEL11

Serial 0D1_DDR2

I2C

Serial 1

SPI-0

Stratix II GX

#2

RLDRAM

64MB

Local Bus

Addr/Data

COP/

JTAG

Serial CFG

EEPROM

RLDRAM

64MB

P1 DDR

SDRAM

P2 DDR2

SDRAM

RLDRAM

64MB

RLDRAM

64MB

I2C

EEPROM

RLDRAM

64MB

RLDRAM

64MB

RLDRAM

64MB

RLDRAM

64MB

Stratix II GX

#1

Stratix II GX

#4

I2CI2C

Stratix II GX

#3 Cavium

Octeon

CN5860

Processor 2

Serial 0

Serial 1

D1_DDR2

I2C

SPI-1

SPI-0

Local Bus

Addr/Data

PCI

Bus

IDSEL12

Cavium Processor Complex 1 Cavium Processor Complex 2

NOR

Flash

4M x8

Socketed

ROM

512K x8

NOR

Flash

4M x8

Socketed

ROM

512K x8

Contents

Main Page Regulatory Agency Warnings & Notices FCC RULES AND REGULATIONS PART 15 EMC COMPLIANCE GR-1089-CORE STANDARD Regulatory Agency Warnings & Notices EC Declarat ion of Conf ormity Page Page Contents 1Overview 2Setup Insert a board: . . . . . . . . . 2-11 Remove a board: . . . . . . . 2-11 3 Cavium Processor Complex 6 Ethernet Interface 7 System Management 8 Back Panel Connectors 9 Management Processor Monitor 10Acronyms Figures Page Tab les Page Tab les Page Registers Page Section 1 Overview COMPONENTS AND FEATURES Page Overview: 10009109-01 ATCA-9305 Users Manual 1-3 FUNCTIONA L OVERV IEW The following block diagram provides a functional overview for the ATCA-9305: Figure 1-1: General System Block Diagram ADDITIONAL INFORMATION Product Certification RoHS Compliance Terminology and Notation Technical References Device / Interface: Document: 1 (continued) Page Section 2 Setup ELECTROSTATIC DISCHARGE ATCA-9305 CIRCUIT BOARD Page 10009109-01 ATCA-9305 Users Manual 2-3 Figure 2-2: Component Map, Top (Rev. 01) CR26 C641 CR17 C643 Setup: 2-4 ATCA-9305 Users Manual 10009109-01 Figure 2-3: Component Map, Bottom (Rev. 01) C2167 Figure 2-4: LED, Fuse and Switch Locations, Top Figure 2-5: LED and Switch Locations, Bottom Hot Swap Connectors Configuration Header ATCA-9305 SETUP Power Requirements Environmental Considerations Hot Swap TROUB LESH OOTI NG Technical Support Product Repair Comments and Suggestions Page 10009109-01 ATCA-9305 Users Manual 3-1 Section 3 Cavium Processor Complex Figure 3-1: Cavium Processor Complex Bl ock Diagram CAVIUM CN5860 PROCESSOR The main features of the CN5860 include: Table 3-1: CN5860 Features Cavium Memory Map PCI CN5860 Boot Over PCI Cavium Reset Figure 3-2: CN5860 Reset Diagram KSL CPLD Cavium Processor Complex: CAVIUM ETHERNET CAVIUM MONITOR Start-up Display Power-up/Reset Sequence Diagnostic Tests During Power-up and Reset Cavium Environment Variables Bit: The following table lists the standard Cavium environment variables: Diagnostic Test: De scrip tion: Value: Default Value: Description: Cavium Processor Complex: MEMORY DDR2 SDRAM RLDRAM I2C EEPROM Flash, 512 KB x 8 Flash, 4 MB x 16 STRATIXGX INTERCONNECT PLD Registers Page Page Page Cavium Processor Complex: HEADERS AND CONNECTORS COP/JTAG Headers Cavium Processor Complex: Console Serial Ports (optional) Page Section 4 Management Complex Figure 4-1: MPC8548 Management Processor Complex Block Diagram MPC8548 PROCESSOR MPC8548 Memory Map Figure 4-2: MPC8548 Memory Map Table 4-2: MPC8548 Address Summary Hex Physical Address: Access Mode: Register Description: See Page: Hex Physical Address: Access Mode: Register Description: (continued) See Page: Chip Selects Reset Diagram Figure 4-3: MPC8548 Reset Diagram KSL CPLD Management Complex: MEMORY SDRAM Flash Management Complex: PCI PCI Express Management Complex: I2C INTERFACE MANAGEMENT PROCESSOR HEADER AND SERIAL PORT JTAG/COP Interface (optional) Management Complex: Pin: Signal: Description: (continued) Serial Debug Port Pin: Signal: Section 5 Management Processor CPLD MPC8548 PLD REGISTER SUMMARY Product ID This read-only register identifies the board as ATCA-9305, and is used for PLD coding. Hardware Version This read-only register tracks hardware revisions. Bits: Function: Description: PLD Version PLL Reset Configuration Hardware Configuration 0 Jumper Settings LED Bits: Function: Description: Reset Event Reset Command 1 Reset Command 2 Reset Command 3 Reset Command 4 Reset Command 5 Reset Command Sticky #1 Reset Command Sticky #2 Boot Device Redirection Miscellaneous Control This register includes two bits for manually toggling the MPC8548 I2C bus. Low Frequency Timer 1 and 2 Bits: Function: Description: RTM GPIO State This read-only register reads the current state of the GPIO pins. The RTM identification (ID) is determined by factory installed configuration resistors. RTM GPIO Control RTM Status Cavium 1 C_MUL Clock Divisor Control Cavium 2 C_MUL Clock Divisor Control Bits: Function: Description: JTAG Cavium GPIO Control Cavium GPIO Data Out Bits: Function: Description: (continued) This register is the data that will be driven on the GPIO line when the Output enable is set. Cavium GPIO Data In This register reads the value on the GPIO lines connected to each Cavium. IPMP/IPMC GPIO Control LPC Bus Control LPC Data Serial IRQ Interrupt 1 Serial IRQ Interrupt 2 Page Section 6 Ethernet Interface BROADCOM BCM56802 SWITCH ETHERNET SWITCHING Ethernet Interface: Figure 6-1: Ethernet Switching Interface Diagram Ethernet Transceivers Ethernet Switch Ports Table 6-1: Ethernet Switch Ports Ethernet Interface: VLAN Setup MPC8548 MANAGEMENT PROCESSOR ETHERNET ADDRESS Ethernet Interface: Front Panel Ethernet Ports Page Page Section 7 System Management IPMC OVERVIEW IPMI MESSAGING Hex Code Value(s): Name: Type: Name: IPMI Completion Codes Code: Description: System Management: IPMB PROTOCOL System Management: SIPL PROTOCOL System Management: Figure 7-2: Extension Command Request Example Figure 7-3: Extension Command Response Example MESSAGE BRIDGING [B8 00 01 0A 40 00 12] Page System Management: STANDARD COMMANDS System Management: Command: (continued) netFn: LUN: Cmd: System Management: OEM BOOT OPTIONS IPMC WATCHDOG TIMER COMMANDS Watchdog Timer Actions Watchdog Timer Use Field and Expiration Flags Watchdog Timer Event Logging Reset Watchdog Timer Command Set Watchdog Timer Command Page Get Watchdog Timer Command Type: Byte: Data Field: (continued) FRU LEDS Get FRU LED Properties Command This command allows software to determine which LEDs are under IPMC control. Get LED Color Capabilities Command Page Set FRU LED State Command Get FRU LED State Command Page VENDOR COMMANDS Command: netFn: LUN: Cmd: Get Status Page Get Serial Interface Properties Type: Byte: Data Field: Set Serial Interface Properties Type: Byte: Data Field: Get Debug Level The Get Debug Level command gets the current debug level of the IPMC firmware. Set Debug Level The Set Debug Level command sets the current debug level of the IPMC firmware. Type: Byte: Data Field: Get Hardware Address The Get Hardware Address command reads the hardware address of the IPMC. Set Hardware Address Type: Byte: Data Field: Get Handle Switch Set Handle Switch Get Payload Communication Time-Out Set Payload Communication Time-Out Enable Payload Control Disable Payload Control Reset IPMC Hang IPMC Bused Resource Bused Resource Status Graceful Reset Type: Byte: Data Field: Diagnostic Interrupt Results Get Payload Shutdown Time-Out Set Payload Shutdown Time-Out Set Local FRU LED State The Set Local FRU LED State command is used to change the local state of a FRU LED. Type: Byte: Data Field: Get Local FRU LED State The Get Local FRU LED State command is used to read the local state of a FRU LED. Type: Byte: Data Field: Update Discrete Sensor Update Threshold Sensor Type: Byte: Data Field: System Management: BOOT DEVICE REDIRECTION (BDR) System Management: Figure 7-4: Boot Device Diagram Payload Management Controller Payload Reset System Management: MESSAGE LISTENERS System Management: Add Message Listener Remove Message Listener System Management: Get Message Listener List SYSTEM FIRMWARE PROGRESS SENSOR Type: Byte: Data Field: System Management: ENTITIES AND ENTITY ASSOCIATIONS Page System Management: SENSORS AND SENSOR DATA RECORDS Page System Management: FRU INVENTORY System Management: E-KEYING System Management: Base Point-to-Point Connectivity HPM.1 FIRMWARE UPGRADE System Management: HPM.1 Reliable Field Upgrade Procedure IPMC HEADERS Page Section 8 Back Panel Connectors ZONE 1 Back Panel Connectors: ZONE 2 Pin: Signal: Insertion Sequence: Back Panel Connectors: ZONE 3 Row: Interface: AB: CD: EF: GH: A: B: C: D: E: F: G: H: Back Panel Connectors: A: B: C: D: E: F: G: H: Pin: A: B: C: D: Section 9 Management Processor Monitor COMMAND-LINE FEATURES Management Processor Monitor: Figure 9-1: Example MPC8548 Monitor Start-up Display Table 9-1: Debug LED Codes LED Code: Power-up Status: LED Value: BOARD_PRE_INIT start booting, setup BATs done 0x01 SERIAL_INIT console init done 0x02 Management Processor Monitor: BASIC OPERATION Power-up/Reset Sequence Management Processor Monitor: Figure 9-2: Power-up/Reset Sequence Flowchart POST Diagnostic Results Management Processor Monitor: Monitor SDRAM Usage MONITOR RECOVERY AND UPDATES Management Processor Monitor: Recovering the Monitor Resetting Environment Variables Updating the Monitor via TFTP Management Processor Monitor: MONITOR COMMAND REFERENCE Command Syntax Page bootv bootvx dhcp rarpboot tftpboot Management Processor Monitor: FILE LOAD COMMANDS loadb loads MEMORY COMMANDS Management Processor Monitor: cmp cp find md Management Processor Monitor: mm nm mw Management Processor Monitor: FLASH COMMANDS cp erase flinfo Management Processor Monitor: protect EEPROM/I2C COMMANDS eeprom Management Processor Monitor: icrc32 iloop imd imm Management Processor Monitor: iprobe IPMC COMMANDS bootdev fru Management Processor Monitor: fruinit fruled ipmchpmfw sensor Management Processor Monitor: ENVIRONMENT PARAMETER COMMANDS printenv saveenv setenv Management Processor Monitor: Page help iminfo isdram loop memmap pci phy ping reset run script showmac sleep switch_reg version vlan Management Processor Monitor: MPC8548 ENVIRONMENT VARIABLES Default Value: Desc ription : Management Processor Monitor: Default Value: Desc ription : (continued) Management Processor Monitor: TROUB LESH OOTI NG DOWNLOAD FORMATS Management Processor Monitor: Binary Motorola S-Record Page Section 10 Acronyms Acronyms: Index A B C E Index N P R S Page Page Notes