CHAPTER 1
KEY CCNCEPTS
This chapter introduces the iAPX 432 Interface Processor (IP). The first four sections cover the IP as it is used normally in connection with inIXlt/output operations. Section 1-1 distinguishes Peripheral Subsystems (PS), which are responsible for the bulk of I/O operations, fran the 432 data processing system, and shows how
Interface Processors link these together. The second section reviews the 432' s basic model of inp.lt/outp,lt, pointing out the need for an interface between a Peripheral Subsystem and the 432 system. Section 1-3descr ibes the hardware and software that conpr ise this Peripheral Subsystem interface, with particular emphasis on the role of the IP. In the fourth section the I/O roc>del i.s summar ized and a simple example ~lementation is reviewed. The final section of the chapter introduces physical reference m::>de and interconnect addressing, two additional IP facilities that are provid.ed for special situations.
1-1.PERIPHERAL SUBSYSTEMS
A typical application based on the iAPX 432 microprocessor family consists of a 432 .system and one or more satellite Peripheral
Subsystems. Figure 1-1 illustrates a hypothetical configuration which employs two Per ipheral Subsystems. The 432 system hardware is composed of one or more iAPx 432 General Data Processors (GDPs), one or more Interface Processors, and a COII1I'OC>n memory which is shared by these processors. The 432 system software is a collection of one or more processes which execute on the GDP(s).
A fundamental principle of the 432 architecture is that the 432 system environment is seIf-contained.; neither processors nor processes have any direct oontact with the "outside world."
Conceptually, the 432 system is enclosed by a wall that protects objects in memory from possible damage by uncontrolled I/O oper.ations.
