Intel iapx 432 manual Peripheral Subsystem Interface Hardware

1-3. PERIPHERAL SUBSYS'lm INTERFACE

A Peripheral Subsystem interface is a collection of hardware and software that acts as an ad.aptor which enables message-based oammunication between a process in the 432 system and a device task in a Peripheral Subsystem. Viewed from the 432 side, the Peripheral

Subsystem interface appears to be a set of processes. The Peripheral Subsystem interface may be designed to present any desired appearance to a device task. For example, it may look like a collection of tasks.

PERIPHERAL SUBSYSTEM INTERFACE HARDWARE

The Peripheral Subsystem interface hardware consists of a 432 Interface Processor, an Attached Processor (AP), and tnem:)ry (see figure 1-4).To improve performance, these may be augmented by a

~ controller. The AP and the IP provide complementary facili ties. Considered as a whole, the AP/IP pair may be thought of as a logical I/O processor, which supports software operations in both the 432 system and the Peripheral Subsystem.

ATrACHED PIU:X'3SOR

Most any general-purpose processor, such as an 8085, an iAPX 86 or an iAPX 88, can be used as an Attached Processor. The AP need not be dedicated exclusively to working with the Interface Processor. It may, for example, also execute device task software or user

applications. Thus, the AP may be the only processor in the Peripheral Subsystem, or it may be one of several. 'lb insure synchronization and coordination, in Peripheral Subsystems with multiple processors, only one of these should be designated to serve

as the AP. Other processors (or active agents, such as IJ.V\. controllers) may be given access to IP windows, but control of the Interface Processor should be centralized in the Attached Processor.

As figure 1-4shows, the AP is "attached" to the Interface Processor in a logical sense only. The physical connections are standard bus signals and one interrupt line (which would typically be routed to the AP via an interrupt controller).

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