KEY CCHE?TS
In a
A Peripheral Subsystem resembles a conventional mainframe channel in that it assumes responsibility for l~level I/O device su~rt and executes in parallel with 432 system processor(s). Unlike a simple channel, however, each Peripheral Subsystem can be configured with a complement of hardware and software resources that precisely fits
application cost am performance requirements. In general, any system that can oonmunicate over a standard 8- or
A Peripheral Subsystem is attached to the 432 system by means of an
iAPX 432 Interface Processor (IP). At the hardware level, an Interface Processor presents two separate bus interfaces. One of these is the standard 432 processor packet bus and the other is a very general interface that can be adapted to nost traditional 8- and
The Interface Processor is driven by Peripheral Subsystem software. 'lb sUQ?Ort the transfer of information through the wall that separates a Peripheral Subsystem from the 432 system, the IP provides a set of
Subsystem. Tb preserve the integrity of the
An Interface Processor additionally provides a set of functions, which are also invoked by Peripheral Subsystem software. While the operation of these functions (and the returned results) varies considerably, they generally permit objects in 432 system memory to be manipulated as entities, and enable conmunication between 432 system processes and software executing in a Peripheral Subsystem.