Intel iapx 432 manual System 0BJECrS Structures

SYSTEM 0BJECrS STRUCTURES

The base rights field of a processor access segment access descriptor is interpreted in the same manner as for all objects of base type access segment. The la-l order bit of the system rights field of a processor access descriptor is interpreted as follows:

o - an interprocessor message may not be broadcast via the global communication segment of this processor

I - an interprocessor message may be broadcast via the global oommunication segment of this processor

The mid order bit of the system rights field of a processor access descriptor is interpreted as follows:

o - an interprocessor message may not be sent to this processor

via the local communication segment of this processor 1 - an interprocessor message may be sent to this processor

via the local communication segment of this processor

The high order bit of the system rights field of a processor access descriptor is uninterpreted.

Processor Data Segments

The intended use of this data segment is as instance specific control information, for recording a copy of the processor-resident information contained in the function request facility and the mapping facility, for recording fault information, and as randomly addressable scalar working storage. The ropy of processor-resident info~ation in the processor data segment is updated by the processor whenever a signif icant state change to that information occurs (i.e., function completion or block transfer canpletion). The area above double byte displacement four is made visible to Attached Processor software through the control window (window 4).

The information in the processor data segment is organized as shown in the diagram below.

A-9