• | n | 'it' | CHAPTER 5 |
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| PHYSICAL REEKRENCE MJOE |
The preceding chapters of this manual have Dmplicitly described the Interface Processor's logical reference node, its mrmal nnde of operation. The IP also provides ptzsical reference mode. Physical
reference mode is distinguished rom logical reference mode by direct
An Interface Processor can switch from physical reference mode to logical reference mode (and vice versa) only under carefully controlled circumstances.
An Interface Processor enters physical reference mode in response to assertion of its INIT line dur ing system initialization (see iAPX 43203 VLSI Interface Processor Data Sheet, Order No. 171874) or upon receiving an "enter physical reference mode" IPC when in logical node. Sioce a "send to processor" IPC requires an access descriptor with the proper right for the target processor's processor object, the ability of 432 software to place an IP in physical reference mode can be l~ited by restricting distributioo of this right in IP
processor object references. However, any 432 process with an access descr iptor for a processor obj ect . with "broadcast to processors" rights can place all IPs into physical mode by
broadcasting the "enter physical reference mode" IPC. Thus, processors should only be granted broadcast rights with careful precautions. Table
An Interface Processor exits physical reference nnde and enters logical reference mode when it receives a local IPC (it ignores global IPCs in physical IlPde). This local IPC is considered a startup IPC. The response of IP is to qualify the processor, enter logical node, and then respond to the IPC.