Intel® PXA27x Processor Family Power Requirements
4.4Power Manager I2C Data (PWR_SDA) / GPIO<4>)
The PWR_SDA signal is the power manager I2C data signal to the external PMIC. It functions like an open-drain signal so either component can pull it down to a logic-low level.
4.5System-Level Considerations for I2C
Both I2C signals have an alternate function on the PXA27x processor as GPIO signals. Following cold-start power-on or a hard reset, both signals default to the GPIO mode of operation and are configured as inputs. An internal (nominally 50 KΩ) pull-down resistor on each signal prevents them from floating during reset or power-on events. To use the I2C capabilities after power-up or reset, the PXA27x processor must, while under software control, configure these signals as I2C signals and disconnect the internal pull-down resistor.
These I2C signals behave functionally like open-drain outputs and require an external pull-up resistor on the system module in the 2 KΩ to 20 KΩ range1. A typical system uses approximately a 5 KΩ resistor connected to 3.3 V.
The I2C signals from the PXA27x processor are pulled low after power-up or reset events. The PMIC must ignore those signals (logic low is the asserted or ON state for I2C bus) after either type of event until the PXA27x processor has asserted PWR_EN and SYS_EN, and the system is operating normally.
The I2C interface does not support the hardware general call, 10-bit addressing, high-speed mode (Hs-mode, 3.4 Mbits/s), or CBUS compatibility. Although other compatible protocols, such as SMBus, can be used with the PXA27x processor I2C interface, they have not been tested for compatibility.
Refer to the I2C Bus Interface Unit section of the Intel® PXA27x Processor Family Developer’s Manual for more information.
4.6On, Off, and RESET
4.6.1On and Off Control
User-initiated ON and OFF events are accomplished using a push button or similar type of system power switch. The system power switch is a momentary-contact type; making contact shorts the normally high input to GND.
The switch signal can be connected directly to a PXA27x processor GPIO input or, preferably, to the PMIC, which debounces the input and forwards the clean signal to a PXA27x processor GPIO. This process requires two signals on the PMIC; one input and one output. GPIO<0> or GPIO<1> are recommended for this purpose because they can generate deep-sleep wake-up events.
4.6.2User-Initiated Hard Reset Input
This signal from a momentary-contact push button switch connects to a power controller input for user-initiated hard reset. Detection of hard reset forces assertion of the nRESET output from the power controller IC to the PXA27x processor. The input must be debounced to cause clean
1.See I2C-Bus Specification 2.1, dated January 2000, by Phillips Semiconductors, order #9398 358 10011, pp. 39-42.
