![6.0Dynamic Voltage Management (DVM)](/images/new-backgrounds/103279/10327957x1.webp)
Intel® PXA27x Processor Family Power Requirements
Note: If the PMIC does not disable VCC_CORE, VCC_PLL, or VCC_SRAM when PWR_EN is de- asserted, the PMIC must not disable any of the regulators controlled by SYS_EN when SYS_EN is
A wakeup event must occur to exit deep sleep. The wakeup event can include the following:
•A transition on one of the deep sleep
•An interrupt from a timer in the
Upon exiting from
The PXA27x processor asserts SYS_EN to the PMIC and starts its SYS_DEL timer. The PMIC turns on its
Note: If the nBATT_FAULT signal asserts in sleep or deep sleep, all
If the
6.0Dynamic Voltage Management (DVM)
The PXA27x processor has a number of features that enable the dynamic management of power consumption, which is based on the computing power required at any particular time. These features enable the processor to modify the core frequency voltage of the processor during operation, dynamically matching the computing performance to the current computing workload. A system combining the PXA27x processor, a power management integrated circuit (PMIC), and supporting DVM software can run a wide range of applications using only a fraction of the battery power that would be required running at the fixed frequency and voltage needed for the peak computing workload.
6.1VCC_CORE Regulator and Dynamic Voltage Management
The PMIC must have these minimum features for its VCC_CORE regulator to support dynamic voltage and frequency management:
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Application Note | 29 |