Intel PXA27X manual Sleep and Deep Sleep, Sleep Entry and Exit

Intel® PXA27x Processor Family Power Requirements

5.2Sleep and Deep Sleep

The sleep and deep-sleep modes reduce power consumption by powering down most units in the PXA27x processor. However, the real-time clock, timekeeping oscillator (32.768 kHz), and PMU circuits remain active. The processor oscillator (13.000 MHz), power manager I2C, and JTAG units may also be active. One, two, or four banks of internal SRAM can (optionally) remain powered in sleep mode to retain data, at the expense of approximately 100 ∝W per bank.

In sleep and deep-sleep modes, the PXA27x processor power supplies VCC_CORE, VCC_SRAM, and VCC_PLL can be disabled to achieve greater system power savings. In deep- sleep mode, the system power supplies VCC_IO, VCC_LCD, VCC_USIM, VCC_BB, VCC_USB, and VCC_MEM can also be powered down for additional power savings. The PXA27x processor then uses VCC_BATT to power an internal DC-to-DC converter, optimized for high efficiency at low power, to create the internal supplies.

The penalty for removing power from VCC_CORE and VCC_SRAM is that the processor execution state is lost. Once the processor activity has stopped, recovery from sleep and deep-sleep modes must be through an external wakeup event or a real-time clock timer event that initiates a sleep reset sequence to boot the PXA27x processor again.

Retaining SDRAM contents while in sleep and deep-sleep modes requires an additional, efficient low-current supply powered from either the main or backup battery. Pull down the PXA27x processor SDCKE signal to retain SDRAM contents while in sleep and deep sleep.

Before entering the sleep or deep-sleep modes, software must program the appropriate registers within the PXA27x processor to:

•Set up delay timers

•Shut off internal functional blocks

•Specify the wakeup sources for exiting sleep or deep sleep

Software initiates entry into sleep or deep sleep (for example, the user presses the OFF button and closes the unit cover), or by a hardware event such as assertion of the nVDD_FAULT or nBATT_FAULT signals from the PMIC. See Section 7.0 for fault conditions and interaction between the PXA27x processor and the PMIC during those events.

5.2.1Sleep Entry and Exit

Prior to entering sleep mode, the PXA27x processor prepares the PMIC by specifying which additional system regulators, if any, are to be disabled or shut down when the PMIC is commanded to go into sleep mode. The set of regulators to be turned off can be fixed in PMIC hardware, or it might be programmable. If programmable, a register in the PMIC is loaded via I2C to specify which regulators turn off. For optimal power savings during sleep, enable and disable the VCC_CORE, VCC_PLL, and VCC_SRAM regulators using PWR_EN, but other regulators in the system may or may not require enabling/disabling, depending upon system design. For example, if a memory device or peripheral must retain its contents during sleep under certain conditions, it may require another regulator that is software controllable.

The PXA27x processor places DRAM memory into self-refresh mode. Note that in self-refresh mode, the DRAM must still be powered, but power decreases substantially. Alternatively, if DRAM contents do not need to be preserved, the processor places the DRAMs into deep-power- down mode. Doing so reduces DRAM power to microamps, even though voltage from the PMIC is still maintained on the DRAM power signals.

Application Note 27