Intel PXA27X manual Hardware Reset Behavior, Intel PXA27x Processor Family Power Requirements

Intel® PXA27x Processor Family Power Requirements

Note: The nRESET signal must be asserted earlier in the reset sequence for the processor. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for power-on reset timing specifications.

The sequence for initial (start-of-life) power-on reset is as follows:

1.VCC_BATT power is applied to the processor and reaches a stable voltage of at least 2.25 V (initiating the power-on reset event) with nRESET asserted from PMIC to the processor.

2.The PMIC must assert nBATT_FAULT because the main battery is not installed.

3.The PMIC de-asserts nRESET after a minimum of 50 ms.

4.The PXA27x processor enables its internal PMU, which waits for the de-assertion of nBATT_FAULT to indicate main battery installation.

5.The fully charged main battery is installed and the PMIC de-asserts nBATT_FAULT.

6.The PXA27x processor asserts SYS_EN to enable the system high-voltage I/O power supplies. The PXA27x processor starts its SYS_DEL countdown timer set to the default 125 ms period.

7.The PMIC enables the regulators driving VCC_IO, and then VCC_LCD, VCC_MEM, VCC_USIM, VCC_BB, and VCC_USB. The latter regulators power on and achieve regulation in any order.

8.After the 125 ms SYS_DEL timer expires, the PXA27x processor asserts PWR_EN to enable the PXA27x processor low-voltage power supplies. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for Power-On reset timing specifications. The PXA27x processor starts its PWR_DEL countdown timer set to the default 125 ms period.

9.The PMIC enables the regulators driving VCC_CORE, VCC_PLL, and VCC_SRAM. These regulators power on and achieve regulation in any order.

10.The PMIC de-asserts nVDD_FAULT when all supplies are stable and within regulation specifications.

11.After the 125 ms PWR_DEL timer expires, the PXA27x processor samples the

nVDD_FAULT input. If nVDD_FAULT is asserted, the PXA27x processor returns to sleep or deep-sleep mode; otherwise, the sequence continues.

12.The PXA27x processor continues its power up initialization by enabling the processor (13.000 MHz) oscillator and internal PLLs and switching the I/O supply power for the internal domains from VCC_BATT to VCC_IO.

13.The PXA27x processor de-asserts the nRESET_OUT signal and begins the execution of code from the reset vector.

Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for power-on reset timing specifications.

5.1.3Hardware Reset Behavior

Hardware reset initiates when the PMIC asserts the nRESET signal low. On assertion of nRESET, the PXA27x processor enters hardware reset state and asserts nRESET_OUT. The PMIC must hold nRESET low long enough to allow internal stabilization and propagation of the reset state, which is a minimum of 50 ms.

The sequence for hardware reset is as follows:

24 Application Note