Intel PXA27X manual Programmable Voltage Control, DVM Control Register, Application Note

Intel® PXA27x Processor Family Power Requirements

•USB on-the-go charge pump which generates +5.0 V (optional)

The following analog/mixed-signal features are required in many handheld or battery-powered systems, and it is a good idea to provide them in a highly integrated PMIC:

•Power supply for LCD panels or other display types

•USB host VBUS (+5 V) power output

•Power supply for CMOS or CCD image sensor

•Touchscreen controller

•Stereo audio CODEC

•Headset amplifier

•Buzzer/vibration motor driver

•LED drivers

•General purpose input/output (GPIO) signals

•Temperature sensor

8.3Programmable Voltage Control

Maintaining the functionality of the PXA27x processor during any VCC_CORE voltage change (static or dynamic) requires a special external voltage regulator, which must have the features described in Section 6.1. These features are configured through a set of control registers like those described in the following subsections. The PMIC can contain additional registers to control additional system regulators and to provide status bits for system regulators whose voltage is configured by strapping hardware control signals.

8.3.1DVM Control Register 1

This 8-bit register specifies the target voltage for VCC_CORE. The specific bit encoding is left to the PMIC designer. The output of the regulator for VCC_CORE must not go below 0.85 V or above 1.55 V (±10%) regardless of the value set in this register.

Note: This regulator output threshold may be higher depending upon the scope of operation of the PMIC. Refer to Section 6.1 of this document for more information.

8.3.2DVM Control Register 2

This 4-bit to 8-bit register controls the voltage ramp rate. The specific bit encoding is left to the PMIC designer. This register might contain a time delay value that controls the time between output voltage microsteps in implementations that use a discrete voltage ramp rate mechanism. During a voltage change, the regulator output is stepped from the initial voltage to the new set point one microstep at a time to achieve a controlled voltage ramp rate. The input clock is expected to be in the range of 500 kHz to 1 MHz, so it can count out intervals with a minimum of 2 ∝s for each voltage microstep, but the exact delay depends upon the size of the voltage steps used.

34 Application Note