Intel® PXA27x Processor Family Power Requirements
Figure 3. Overview of Power Management Operating Modes
| any reset | Reset Mode |
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Idle |
| Normal Mode | Sleep | ||
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CPDIS=1 |
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| Idle |
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| instruction | Standby |
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Interrupt | CPDIS=0 | OR (Fault & xIDAE=1) | |||
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OR (Fault & xIDAE=1) |
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| OR (Fault & xIDAE=1) |
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| OR (Fault & xIDAE=1) | ||
Deep Idle Mode | Idle Mode | Standby Mode | Sleep Mode | ||
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| Fault & xIDAE=0 | Fault & xIDAE=0 | |
| Fault & xIDAE=0 |
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Fault & xIDAE=0 |
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| Deep Sleep Mode | |
4.0Power Controller Interface Signals
The PXA27x processor has an internal power manager unit (PMU) and a set of I/O signals for communicating with an external power management integrated circuit (PMIC). These signals are active for initial power up, certain reset events, device on/off events, and transitions between some operating modes. In addition, two fault signals are required from the PMIC to communicate the onset of power supply problems to the processor. These signals and their function are described fully in Section 7.0.
The PXA27x processor communicates to the power controller using the signals defined in Table 8.
18 | Application Note |
