Intel PXA27X Power Mode Sequencing, Cold-Start Power-On and Hardware Reset, Application Note

Intel® PXA27x Processor Family Power Requirements

The PXA27x processor has a low-power DC-to-DC converter that is enabled by software while in sleep or deep-sleep mode. Enabling the low-power DC-to-DC converter further reduces power consumption by shutting off the high-power regulators on the PMIC, eliminating losses in the external power supply subsystem. Use of the sleep mode DC-to-DC converter requires three external capacitors connected to the PXA27x processor PWR_CAP signals.

These capacitors are required for the DC-to-DC converter:

•A 0.1 ∝F capacitor connected between the PWR_CAP<0> and PWR_CAP<1> signals

•A 0.1 ∝F capacitor connected between the PWR_CAP<2> and PWR_CAP<3> signals

A 0.1 ∝F capacitor connected between the PWR_OUT signal and ground is always required. Use ceramic, unpolarized capacitors with a low equivalent series resistance (ESR). No other connections are allowed on the PWR_OUT and PWR_CAP<3:0> signals.

Note: The PWR_CAP signals must not be shared with the GPIO<5:8> functions under any conditions.

5.0Power Mode Sequencing

The PXA27x processor supply voltages must be powered up in a specific sequence to avoid damage to the processor. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for power-on-reset timing specifications. In general, VCC_BATT must be the first domain to be powered on, and the last to be powered off. After that, I/O voltages must be powered on before internal voltages, and powered off after internal voltages are turned off.

I/O voltages are the higher voltages (1.8 V to 3.3 V) that power the I/O cells: VCC_IO,

VCC_LCD, VCC_MEM, VCC_BB, VCC_USB, VCC_USIM. These voltages must power on first (after VCC_BATT powers up), and must be the last to power off (before VCC_BATT powers off).

Internal voltages are those that power the PXA27x processor core, the PLLs, and internal SRAM: VCC_CORE, VCC_PLL, and VCC_SRAM. VCC_CORE ranges from 0.85 V to 1.55 V in normal operation, while VCC_PLL and VCC_SRAM are fixed at 1.3 V and 1.1 V, respectively.

Within the I/O supply group, VCC_IO must be established at or before (but not after) any other supply (except VCC_USB). Within the internal supply group, there is no specific sequencing requirement within the internal supply group. The internal supplies can be turned on or off in any order, or simultaneously. For powering on from a cold start, each domain must not exceed the maximum (quickest) ramp rate specification and the power-on timing requirements should be strictly observed. Refer to the Intel® PXA27x Processor Family EMTS for details.

5.1Power-On

5.1.1Cold-Start Power-On and Hardware Reset

Power-on reset occurs when power is first supplied to the backup battery signal VCC_BATT, following a powered-off condition. All PXA27x processor internal units are reset to a known state exactly like hardware reset. Power-on reset is a complete and total reset that occurs at initial power- on only.

22 Application Note