Freescale Semiconductor MC68HC908MR16 manual Reset and System Initialization, Clocks in Wait Mode

Reset and System Initialization

OSC1				CGMXCLK	SIM COUNTER
	CLOCK	⎟ 2	A	CGMOUT	⎟ 2	BUS CLOCK
	SELECT
CGMVCLK	CIRCUIT		B	S*		GENERATORS
				*When S = 1,
				CGMOUT = B
PLL	BCS					SIM
	PTC2
	MONITOR MODE
	USER MODE
	CGM

Figure 14-2. CGM Clock Signals

14.2.3 Clocks in Wait Mode

In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

14.3 Reset and System Initialization

The MCU has these reset sources:

•Power-on reset module (POR)

•External reset pin (RST)

•Computer operating properly (COP) module

•Low-voltage inhibit (LVI) module

•Illegal opcode

•Illegal address

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states.

An internal reset clears the SIM counter (see 14.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 14.7.2 SIM Reset Status Register.

14.3.1 External Pin Reset

Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 14-2for details. Figure 14-3shows the relative timing.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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