Freescale Semiconductor MC68HC908MR32 manual 17.7 I/O Registers, Timb Status and Control Register

Timer Interface B (TIMB)

17.7 I/O Registers

These input/output (I/O) registers control and monitor TIMB operation:

•TIMB status and control register (TBSC)

•TIMB control registers (TBCNTH–TBCNTL)

•TIMB counter modulo registers (TBMODH–TBMODL)

•TIMB channel status and control registers (TBSC0 and TBSC1)

•TIMB channel registers (TBCH0H–TBCH0L and TBCH1H–TBCH1L)

17.7.1 TIMB Status and Control Register

The TIMB status and control register:

•Enables TIMB overflow interrupts

•Flags TIMB overflows

•Stops the TIMB counter

•Resets the TIMB counter

•Prescales the TIMB counter clock

Address:	$0051
	Bit 7	6	5	4	3	2	1	Bit 0
Read:	TOF	TOIE	TSTOP	0	0	PS2	PS1	PS0
Write:	0			TRST	R
Reset:	0	0	1	0	0	0	0	0
	R	= Reserved

Figure 17-5. TIMB Status and Control Register (TBSC)

TOF — TIMB Overflow Flag

This read/write flag is set when the TIMB counter reaches the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMB overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.

1 = TIMB counter has reached modulo value.

0 = TIMB counter has not reached modulo value.

TOIE — TIMB Overflow Interrupt Enable Bit

This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit.

1 = TIMB overflow interrupts enabled

0 = TIMB overflow interrupts disabled

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

244 Freescale Semiconductor