Data Format | Freescale Semiconductor MC68HC908MR32, MC68HC908MR16

Serial Communications Interface Module (SCI)

Addr.

Register Name

SCI Control Register 1

$0038(SCC1) See page 169.

SCI Control Register 2

$0039(SCC2) See page 171.

SCI Control Register 3

$003A(SCC3) See page 173.

SCI Status Register 1

$003B(SCS1) See page 174.

SCI Status Register 2

$003C(SCS2) See page 176.

SCI Data Register

$003D(SCDR) See page 177.

SCI Baud Rate Register

$003E(SCBR) See page 177.

	Bit 7	6		5	4	3	2	1	Bit 0
Read:	LOOPS	ENSCI		TXINV	M	WAKE	ILTY	PEN	PTY
Write:	LOOPS	ENSCI		TXINV	M	WAKE	ILTY	PEN	PTY
Write:

Reset:	0	0		0	0	0	0	0	0
Read:
Read:	SCTIE	TCIE		SCRIE	ILIE	TE	RE	RWU	SBK
Write:	SCTIE	TCIE		SCRIE	ILIE	TE	RE	RWU	SBK
Write:

Reset:	0	0		0	0	0	0	0	0

Read:	R8	T8		0	0	ORIE	NEIE	FEIE	PEIE

Write:	R			R	R
Write:	R			R	R

Reset:	U	U		0	0	0	0	0	0

Read:	SCTE	TC		SCRF	IDLE	OR	NF	FE	PE

Write:	R	R		R	R	R	R	R	R

Reset:	1	1		0	0	0	0	0	0

Read:	0	0		0	0	0	0	BKF	RPF

Write:	R	R		R	R	R	R	R	R

Reset:	0	0		0	0	0	0	0	0

Read:	R7	R6		R5	R4	R3	R2	R1	R0

Write:	T7	T6		T5	T4	T3	T2	T1	T0

Reset:					Unaffected by reset

Read:	0	0		SCP1	SCP0	0	SCR2	SCR1	SCR0

Write:	R	R				R
Write:	R	R				R

Reset:	0	0		0	0	0	0	0	0

	R	= Reserved				U = Unaffected

Figure 13-3. SCI I/O Register Summary

13.3.1 Data Format

The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 13-4.

8-BIT DATA FORMAT

POSSIBLE

BIT M IN SCC1 CLEAR

PARITY

NEXT

BIT

START

START

STOP

BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT

BIT

9-BIT DATA FORMAT

POSSIBLE

BIT M IN SCC1 SET

PARITY

NEXT

START

BIT

START

BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

STOP

BIT

BIT

Figure 13-4. SCI Data Formats

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

160	Freescale Semiconductor

Image 160

Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Data Format, Serial Communications Interface Module SCI Addr

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.

Contents

MC68HC908MR32 MC68HC908MR16 Page MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Data SheetMC68HC908MR32 MC68HC908MR16 Revision History Revision HistoryDate Revision Description Level Numbers List of Chapters List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Table of Contents Chapter Analog-to-Digital Converter ADC Table of ContentsChapter Clock Generator Module CGM Chapter Configuration Register Config Chapter Computer Operating Properly COP Chapter External Interrupt IRQ Chapter Central Processor Unit CPUChapter Low-Voltage Inhibit LVI Chapter Input/Output I/O Ports Ports Chapter Power-On Reset PORChapter Pulse-Width Modulator for Motor Control Pwmmc Chapter Serial Communications Interface Module SCI Chapter System Integration Module SIM Chapter Serial Peripheral Interface Module SPI Chapter Timer Interface a Tima Chapter Timer Interface B Timb Chapter Development Support Chapter Electrical Specifications Chapter Ordering Information and Mechanical Specifications Chapter General Description FeaturesIntroduction MCU Block Diagram General Description Diagram MCU Block Pin Assignments Pin QFP Pin Assignments Pin Sdip Pin Assignments Pin Assignments Power Supply Pins VDD and VSS Oscillator Pins OSC1 and OSC2External Reset Pin RST CGM Power Supply Pins Vdda and Vssad Analog Power Supply Pins Vddad and Vssad Port a Input/Output I/O Pins PTA7-PTA0Port B I/O Pins PTB7/ATD7-PTB0/ATD0 Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8 Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK PWM Ground Pin Pwmgnd Unimplemented Memory Locations Chapter MemoryReserved Memory Locations Memory Map I/O SectionMemory MC68HC908MR32 Memory Map Memory Map Control, Status, and Data Registers Summary Sheet 1 Memory Addr Control, Status, and Data Registers Summary Sheet 2 Memory Map Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 3 Memory Addr Register Name Control, Status, and Data Registers Summary Sheet 4 Control, Status, and Data Registers Summary Sheet 5 Memory Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 6 Addr Register Name Control, Status, and Data Registers Summary Sheet 7 Control, Status, and Data Registers Summary Sheet 8 Vector Addresses Address Vector Low Random-Access Memory RAM Monitor ROMMonitor ROM Address Vector Flash Memory Flash Flash Control Register Hven High-Voltage Enable Bit Flash Page Erase OperationMass Mass Erase Control Bit Erase Erase Control Bit Flash Mass Erase Operation Flash Program Operation Only bytes which are currently $FF may be programmed Flash Programming Flowchart Flash Block Protection Flash Block Protect Register Stop Mode Wait ModeExamples of Protect Start Address Chapter Analog-to-Digital Converter ADC Functional Description Block Diagram Highlighting ADC Block and Pins Analog-to-Digital Converter ADC Voltage Conversion ADC Port I/O PinsFunctional Description Continuous Conversion Conversion TimeResult Justification Bit Truncation Mode Error Monotonicity I/O Signals Wait ModeInterrupts I/O Registers ADC Voltage In AdvinADC External Connections 6.2 ANx Aien ADC Interrupt Enable Bit ADC Status and Control Register Mux Channel Select Input Select ADC Data Register High ADC Data Register Low ADC Clock Divide Ratio ADC Clock RegisterADC Clock Rate Analog-to-Digital Converter ADC Chapter Clock Generator Module CGM Cgmvclk CGM Block Diagram Clock Generator Module CGM Crystal Oscillator Circuit Phase-Locked Loop Circuit PLLPLL Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Variable Definitions Programming the PLLVariable Definition Base Clock Selector Circuit Special Programming Exceptions CGM External Connections CGM External Connections PLL Analog Power Pin Vdda Oscillator Enable Signal SimoscenCrystal Amplifier Input Pin OSC1 Crystal Amplifier Output Pin OSC2 Crystal Output Frequency Signal Cgmxclk CGM RegistersCGM Base Clock Output Cgmout CGM CPU Interrupt Cgmint PLL Control Register Pllf PLL Interrupt FlagPllon PLL On Bit BCS Base Clock Select Bit Lock Lock Indicator Bit ACQ Acquisition Mode BitPLL Bandwidth Control Register PCTL30 Unimplemented Bits PLL Programming Register XLD Crystal Loss Detect BitPBWC30 Reserved for Test VCO Frequency Multiplier N Selection VRS74 VCO Range Select Bits Interrupts Acquisition/Lock Time Definitions Acquisition/Lock Time SpecificationsParametric Influences on Reaction Time Choosing a Filter Capacitor Acquisition/Lock Time SpecificationsReaction Time Calculation Frequency Chapter Configuration Register Config Configuration Register COP Block Diagram Chapter Computer Operating Properly COP Power-On Reset Internal ResetReset Vector Fetch Copctl Write Monitor Mode Stop ModeCopd COP Disable COP Control Register Freescale Semiconductor Chapter Central Processor Unit CPU CPU Registers Index Register AccumulatorCentral Processor Unit CPU Program Counter Stack PointerCPU Registers Condition Code Register Half-Carry FlagInterrupt Mask Negative Flag Low-Power Modes Arithmetic/Logic Unit ALUCPU During Break Interrupts Zero Flag Instruction Set Summary Instruction Set Summary Sheet 1 Instruction Set Summary Instruction Set Summary Sheet 2Source Operation Description On CCR Form Instruction Set Summary Sheet 3 Dbnz opr,rel Instruction Set Summary Sheet 4 JMP ,X Instruction Set Summary Sheet 5 Operation Description On CCR Form Instruction Set Summary Sheet 6 Opcode MapOpcode Map Opcode Map 9ED 9EE IRQ Module Block Diagram Chapter External Interrupt IRQ IRQ Pin External Interrupt IRQ IRQ Interrupt Flowchart IRQ Pin IRQ Status and Control Register IRQ Status and Control Register Iscr Irqf IRQ Flag IRQ Status and Control Register Freescale Semiconductor LVI Module Block Diagram Chapter Low-Voltage Inhibit LVI Forced Reset Operation False Reset ProtectionPolled LVI Operation LVI Trip Selection LVI Status and Control Register LVI InterruptsLviout Bit Indication LVI Status and Control Register 100 Freescale Semiconductor Chapter Input/Output I/O Ports Ports I/O Port Register Summary Input/Output I/O Ports Ports Addr Register Name Port a Port a Data RegisterData Direction Register a Port a Port B Port B Data RegisterPort a Pin Functions Input/Output I/O Ports Ports Port B Pin Functions Data Direction Register BPort B Port C Data Register Port CData Direction Register C Port D Port C Pin FunctionsPort D PTC60 PTD Bit Pin Mode Accesses to PTD Read Port EPort E Data Register Port D Pin Functions Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTE Data Direction Register EPort E Pin Functions Port E Port F Data Register Port FData Direction Register F Port F Pin Functions Port F 112 Freescale Semiconductor Chapter Power-On Reset POR 114 Freescale Semiconductor Chapter Pulse-Width Modulator for Motor Control Pwmmc Block Diagram Highlighting Pwmmc Block and Pins Pulse-Width Modulator for Motor Control Pwmmc PWM Module Block Diagram Features Register Summary Sheet 2 Features Addr Register Name Bit Register Summary Sheet 3 Resolution Timebase Edge-Aligned PWM Positive Polarity Timebase PWM Generators PrescalerLoad Operation PWM Prescaler Reload Frequency Change PWM Interrupt Requests Center-Aligned PWM Value Loading PWM Data Overflow and Underflow Conditions PWM Data Overflow and Underflow ConditionsPWMVALxHPWMVALxL Condition PWM Value Used 12. Complementary Pairing Output Control Dead-Time Insertion Output Control 14. Dead-Time Generators 15. Effects of Dead-Time Insertion 17. Dead-Time and Small Pulse Widths Current Sense Pins Current Voltage On Current Correction Methods Current Correction Bits Correction Method ISENS1 and ISENS0 Output Polarity 20. Top/Bottom Correction for PWMs 1 21. PWM Polarity PWM Output Port Control OUTx Bit Complementary Mode Independent ModeOUTx Bits 23. Dead-Time Insertion During Outctl = Fault Condition Input Pins Fault ProtectionFault Protection 26. PWM Disabling Scheme Fault Pin Filter Automatic Mode 28. PWM Disabling in Automatic Mode Manual Mode Software Output Disable Output Port Control 32. Pwmen and PWM Pins Initialization and the Pwmen Bit PWM Operation in Wait Mode PWM Operation in Wait ModeControl Logic Block PWM Counter Registers PWM Counter Modulo Registers 35. PWM Counter Modulo Register High Pmodh PWMx Value Registers Control Logic Block Disy Software Disable Bit for Bank Y Bit Pwmint PWM Interrupt Enable BitPWM Control Register Pwmf PWM Reload Flag Pwmen PWM Module Enable Bit LDOK- Load OK Bit IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1 IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5 IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3PRSC1 and PRSC0 PWM Prescaler Bits Fault Control Register PWM Disable Mapping Write-Once RegisterDead-Time Write-Once Register FINT2 Fault 2 Interrupt Enable Bit FINT3 Fault 3 Interrupt Enable BitFINT1 Fault 1 Interrupt Enable Bit Fault Status Register Fault Acknowledge Register PWM Output Control Register DT2 Dead-Time 2 BitDT1 Dead-Time 1 Bit 10. OUTx Bits PWM Glossary PWM Glossary 48. PWM Load Cycle/Frequency Definition Chapter Serial Communications Interface Module SCI Block Diagram Highlighting SCI Block and Pins Serial Communications Interface Module SCI SCI Module Block Diagram Data Format Serial Communications Interface Module SCI Addr Transmitter SCI Transmitter Character Transmission Character LengthBreak Characters Receiver Idle CharactersInversion of Transmitted Output Transmitter Interrupts SCI Receiver Block Diagram Character Reception Data Sampling Stop Bit Recovery Data Bit RecoveryStart Bit Verification Framing Errors Error InterruptsReceiver Wakeup Receiver Interrupts SCI During Break Module Interrupts 13.6 I/O Signals13.6.1 PTF5/TxD Transmit Data 13.6.2 PTF4/RxD Receive Data 13.7 I/O RegistersSCI Control Register Ensci Enable SCI Bit Mode Character Length BitPEN Parity Enable Bit Txinv Transmit Inversion Bit Tcie Transmission Complete Interrupt Enable Bit Character Format SelectionControl Bits Character Format Start Data Parity Stop Scrie SCI Receive Interrupt Enable Bit Ilie Idle Line Interrupt Enable BitTE Transmitter Enable Bit RE Receiver Enable Bit Orie Receiver Overrun Interrupt Enable Bit Neie Receiver Noise Error Interrupt Enable BitFeie Receiver Framing Error Interrupt Enable Bit Peie Receiver Parity Error Interrupt Enable Bit TC Transmission Complete Bit SCI Status RegisterScrf SCI Receiver Full Bit Idle Receiver Idle Bit Or Receiver Overrun Bit PE Receiver Parity Error Bit FE Receiver Framing Error BitNF Receiver Noise Flag Bit SCI Data Register SCI Baud Rate RegisterRPF -Reception-in-Progress Flag SCI Baud Rate Prescaling SCI Baud Rate Selection Baud Rate Divisor BD SCI Baud Rate Selection Examples Baud Rate Divisor PD Divisor BD 180 Freescale Semiconductor Signal Name Description Signal Name ConventionsChapter System Integration Module SIM Clock Startup from POR or LVI Reset SIM Bus Clock Control and GenerationBus Timing System Integration Module SIM Reset and System Initialization Clocks in Wait ModeExternal Pin Reset Reset and System Initialization Reset Type Number of Cycles Required to Set PIN Active Resets from Internal SourcesPIN Bit Set Timing Power-On Reset POR Computer Operating Properly COP Reset SIM Counter and Reset States SIM Counter During Power-On ResetSIM Counter Interrupts Exception ControlException Control Interrupt Processing Interrupt Recovery Hardware Interrupts Reset Low-Power ModeSoftware Interrupt SWI Instruction SIM Break Status Register SIM RegistersSIM Registers SIM Reset Status Register PIN External Reset BitIlop Illegal Opcode Reset Bit Ilad Illegal Address Reset Bit opcode fetches only SIM Break Flag Control Register 194 Freescale Semiconductor Pin Name Conventions Chapter Serial Peripheral Interface Module SPIPin Name Conventions Block Diagram Highlighting SPI Block and Pins Serial Peripheral Interface Module SPI SPI Module Block Diagram Master Mode Serial Peripheral Interface Module SPI Addr Slave Mode Clock Phase and Polarity ControlsTransmission Formats Transmission Formats Transmission Format When Cpha = Transmission Format Cpha = Transmission Initiation Latency Transmission Start Delay Master Overflow Error Error ConditionsError Conditions Mode Fault Error 10. Clearing Sprf When Ovrf Interrupt Is Not Enabled Freescale Semiconductor 205 SPI Interrupts Flag Request Resetting the SPI Resetting the SPIQueuing Transmission Data 15.11 I/O Signals 12. SPRF/SPTE CPU Interrupt Timing Signals Miso Master In/Slave OutMosi Master Out/Slave Spsck Serial Clock SPI Configuration SPI Configuration State of SS Logic15.12 I/O Registers VSS Clock Ground Cpha Clock Phase Bit Spwom SPI Wired-OR Mode BitSpmstr SPI Master Bit Cpol Clock Polarity Bit SPE SPI Enable Bit SPTIE- SPI Transmit Interrupt Enable BitErrie Error Interrupt Enable Bit SPI Status and Control Register Modf Mode Fault Bit Modfen Mode Fault Enable BitOvrf Overflow Bit Spte SPI Transmitter Empty Bit SPI Data Register SPI Master Baud Rate Selection Chapter Timer Interface a Tima 2is a block diagram of the Tima Block Diagram Highlighting Tima Block and Pins Timer Interface a Tima Tima Block Diagram Timer Interface a Tima Addr Register Name Bit TIM I/O Register Summary Tima Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Pulse-Width Modulation PWM Buffered Output Compare Unbuffered PWM Signal Generation PWM Period and Pulse Width Buffered PWM Signal Generation PWM Initialization 224 Freescale Semiconductor 16.6 I/O Signals Tima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A16.7 I/O Registers Tima Clock Pin PTE3/TCLKA Trst Tima Reset Bit Toie Tima Overflow Interrupt Enable BitTstop Tima Stop Bit Tima Counter Registers PS20 Prescaler Select BitsPrescaler Selection PS20 Tima Clock Source Tima Counter Modulo Registers Tima Channel Status and Control Registers CHxIE Channel x Interrupt Enable Bit MSxA Mode Select Bit a MSxB Mode Select Bit BELSxB and ELSxA Edge/Level Select Bits MSxBMSxA ELSxBELSxA Mode Configuration Mode, Edge, and Level SelectionTOVx Toggle-On-Overflow Bit CHxMAX Channel x Maximum Duty Cycle Bit Tima Channel Registers 10. Tima Channel Registers 10. Tima Channel Registers TACH0H/L-TACH3H/L 234 Freescale Semiconductor Chapter Timer Interface B Timb Timb module is not available in the 56-pin Sdip Block Diagram Highlighting Timb Block and Pins Timer Interface B Timb Timb Block Diagram Timer Interface B Timb Addr Register Name Bit Timb Counter Prescaler Freescale Semiconductor 239 240 Freescale Semiconductor Freescale Semiconductor 241 242 Freescale Semiconductor Timb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1B 17.6 I/O SignalsTimb Clock Pin PTE0/TCLKB 17.7 I/O Registers Toie Timb Overflow Interrupt Enable BitTimb Status and Control Register Tstop Timb Stop Bit Trst Timb Reset BitPS20 Timb Clock Source Timb Counter Registers Timb Counter Modulo Registers Timb Channel Status and Control Registers 248 Freescale Semiconductor PWM Timb Channel Registers 10. Timb Channel Registers TBCH0H/L-TBCH1H/L Chapter Development Support Break Module BRKFunctional Description Flag Protection During Break Interrupts Break Module Block Diagram Development Support Low-Power Modes Break Module Registers Brka Break Active Bit Break Status and Control RegisterBreak Address Registers Monitor ROM MON Break Status RegisterBreak Flag Control Register Monitor ROM MON Mode Differences Entering Monitor ModeNormal Monitor Mode Monitor Mode Circuit Monitor Mode Signal Requirements and Options $FFFF Forced Monitor Mode Data Format Commands Break SignalEchoing Read Read Memory Command Write Write Memory CommandIread Indexed Read Command Command Sequence Readsp Read Stack Pointer Command Iwrite Indexed Write CommandRUN Run User Program Command Baud Rate SecurityMonitor Baud Rate Selection 13. Monitor Mode Entry Timing Characteristic1 Symbol Value Unit Chapter Electrical SpecificationsAbsolute Maximum Ratings Thermal Characteristics Electrical SpecificationsCharacteristic Symbol Value Unit Functional Operating Range DC Electrical Characteristics DC Electrical CharacteristicsCharacteristic1 Symbol Min Typ2 Max Unit Flash Memory Characteristics Characteristic Symbol Min Typ Max UnitCharacteristic Symbol Min Max Unit Control Timing Serial Peripheral Interface Characteristics Serial Peripheral Interface CharacteristicsDiagram Characteristic2 Symbol Min Max Unit Number1 SPI Master Timing SPI Slave Timing TImer Interface Module Characteristics Clock Generation Module Component SpecificationsCharacteristic Symbol Min Typ Max CGM Operating Conditions CGM Acquisition/Lock Time Specifications CGM Acquisition/Lock Time SpecificationsDescription Symbol Min Typ Max Analog-to-Digital Converter ADC Characteristics 3FF Chapter Ordering Information and Mechanical Specifications Order NumbersOrder Numbers MC Order Number Operating Ordering Information and Mechanical Specifications 20.3 64-Pin Plastic Quad Flat Pack QFP 20.4 56-Pin Shrink Dual In-Line Package Sdip Pin Shrink Dual In-Line Package Sdip 278 Freescale Semiconductor Appendix a MC68HC908MR16 Figure A-1. MC68HC908MR16 Memory Map MC68HC908MR16Page How to Reach Us