Freescale Semiconductor MC68HC908MR16 CGM Registers, Crystal Output Frequency Signal Cgmxclk

CGM Registers

4.4.6 Crystal Output Frequency Signal (CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 4-3shows only the logical relation of CGMXCLK to OSC1

and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup.

4.4.7 CGM Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.

4.4.8 CGM CPU Interrupt (CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

4.5 CGM Registers

These registers control and monitor operation of the CGM:

•PLL control register (PCTL) — see 4.5.1 PLL Control Register

•PLL bandwidth control register (PBWC) — see 4.5.2 PLL Bandwidth Control Register

•PLL programming register (PPG) — see 4.5.3 PLL Programming Register

Figure 4-4is a summary of the CGM registers.

Addr.	Register Name		Bit 7	6	5		4	3	2	1	Bit 0
	PLL Control Register	Read:	PLLIE	PLLF	PLLON		BCS	1	1	1	1
$005C	(PCTL)	Write:		R				R	R	R	R
	See page 66.
		Reset:	0	0	1		0	1	1	1	1
	PLL Bandwidth Control Register	Read:	AUTO	LOCK			XLD	0	0	0	0
						ACQ
		Write:		R				R	R	R	R
$005D	(PBWC)
	See page 67.
		Reset:	0	0	0		0	0	0	0	0
	PLL Programming Register	Read:
			MUL7	MUL6	MUL5		MUL4	VRS7	VRS6	VRS5	VRS4
$005E	(PPG)	Write:
	See page 68.
		Reset:	0	1	1		0	0	1	1	0
				= Reserved
			R

Notes:

1.When AUTO = 0, PLLIE is forced to logic 0 and is read-only.

2.When AUTO = 0, PLLF and LOCK read as logic 0.

3.When AUTO = 1, ACQ is read-only.

4.When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.

5.When PLLON = 1, the PLL programming register is read-only.

6.When BCS = 1, PLLON is forced set and is read-only.

Figure 4-4. CGM I/O Register Summary

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor 65