Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Chapter System Integration Module SIM

Chapter 14

System Integration Module (SIM)

14.1 Introduction

This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities.

A block diagram of the SIM is shown in Figure 14-1.

The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for:

•Bus clock generation and control for CPU and peripherals:

–Wait/reset/break entry and recovery

–Internal clock control

•Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout

•Interrupt control:

–Acknowledge timing

–Arbitration control timing

–Vector address generation

•CPU enable/disable timing

•Modular architecture expandable to 128 interrupt sources

Table 14-1shows the internal signal names used in this section.

	Table 14-1. Signal Name Conventions
Signal Name	Description
CGMXCLK	Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK	Phase-locked loop (PLL) circuit output
CGMOUT	PLL-based or OSC1-based clock output from CGM module (bus clock = CGMOUT divided by two)
IAB	Internal address bus
IDB	Internal data bus
PORRST	Signal from the power-on reset module to the SIM
IRST	Internal reset signal
	Read/write signal
R/W

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor 181