External Interrupt (IRQ)

A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch.

If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and low-level- sensitive. With MODE1 set, both of these actions must occur to clear the IRQ1 latch:

Vector fetch, software clear, or reset — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software can generate the interrupt acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB.

Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set.

The vector fetch or software clear and the return of the IRQ pin to logic 1 can occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0.

If the MODE1 bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ1 latch.

Use the branch if IRQ pin high (BIH) or branch if IRQ pin low (BIL) instruction to read the logic level on the IRQ pin.

NOTE

When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine.

8.5 IRQ Status and Control Register

The IRQ status and control register (ISCR) has these functions:

Clears the IRQ interrupt latch

Masks IRQ interrupt requests

Controls triggering sensitivity of the IRQ interrupt pin

Address:

Read:

Write:

Reset:

$003F

 

 

 

 

 

 

 

Bit 7

6

5

4

3

2

1

Bit 0

 

 

 

 

 

 

 

 

0

0

0

0

IRQF

0

IMASK1

MODE1

 

 

 

 

 

R

R

R

R

ACK1

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

R

= Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8-4. IRQ Status and Control Register (ISCR)

ACK1 — IRQ Interrupt Request Acknowledge Bit

Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1 always reads as logic 0. Reset clears ACK1.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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Freescale Semiconductor

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Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual IRQ Status and Control Register Iscr

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

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