Opcode Map

Table 7-1. Instruction Set Summary (Sheet 6 of 6)

 

 

 

 

 

 

 

 

 

 

 

Effect

 

 

 

 

Address Mode

Opcode

Operand

Cycles

Source

Operation

 

 

Description

 

 

 

 

 

on CCR

 

 

 

 

 

 

Form

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

H

 

I

N

Z

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC (PC) + 1; Push (PCL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP (SP) – 1; Push (PCH)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP

(SP) – 1; Push (X)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SWI

 

Software Interrupt

 

SP

(SP) – 1; Push (A)

 

 

 

 

1

 

 

 

INH

83

 

9

 

 

SP (SP) – 1; Push (CCR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP (SP) – 1; I 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCH Interrupt Vector High Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCL Interrupt Vector Low Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP

 

Transfer A to CCR

 

 

CCR (A)

 

 

 



 



 





 



 



 

INH

84

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAX

 

Transfer A to X

 

 

X (A)

 

 

 

 

 

 

 

 

INH

97

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TPA

 

Transfer CCR to A

 

 

A (CCR)

 

 

 

 

 

 

 

 

INH

85

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TST opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIR

3D

dd

3

TSTA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INH

4D

 

1

TSTX

 

Test for Negative or Zero

 

(A) – $00 or (X) – $00 or (M) – $00

0

 

 



 



 

 

INH

5D

ff

1

TST opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IX1

6D

3

TST ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IX

7D

 

2

TST opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1

9E6D

ff

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSX

 

Transfer SP to H:X

 

 

H:X (SP) + 1

 

 

 

 

 

 

 

 

INH

95

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXA

 

Transfer X to A

 

 

A (X)

 

 

 

 

 

 

 

 

INH

9F

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXS

 

Transfer H:X to SP

 

 

(SP) (H:X) – 1

 

 

 

 

 

 

 

INH

94

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WAIT

 

Enable Interrupts; Wait for Interrupt

 

I bit 0; Inhibit CPU clocking

 

 

 

0

 

 

 

INH

8F

 

1

 

 

 

until interrupted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

Accumulator

 

 

n

Any bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

Carry/borrow bit

 

 

opr

Operand (one or two bytes)

 

 

 

CCR

Condition code register

 

 

PC

Program counter

 

 

 

 

 

 

 

 

dd

Direct address of operand

 

 

PCH

Program counter high byte

 

 

 

dd rr

Direct address of operand and relative offset of branch instruction

PCL

Program counter low byte

 

 

 

 

DD

Direct to direct addressing mode

 

 

REL

Relative addressing mode

 

 

 

DIR

Direct addressing mode

 

 

rel

Relative program counter offset byte

 

 

DIX+

Direct to indexed with post increment addressing mode

 

rr

Relative program counter offset byte

 

 

ee ff

High and low bytes of offset in indexed, 16-bit offset addressing

SP1

Stack pointer, 8-bit offset addressing mode

 

EXT

Extended addressing mode

 

 

SP2

Stack pointer 16-bit offset addressing mode

 

ff

Offset byte in indexed, 8-bit offset addressing

 

 

SP

Stack pointer

 

 

 

 

 

 

 

 

 

 

 

H

Half-carry bit

 

 

U

Undefined

 

 

 

 

 

 

 

 

 

 

 

 

 

H

Index register high byte

 

 

V

Overflow bit

 

 

 

 

 

 

 

 

 

 

 

hh ll

High and low bytes of operand address in extended addressing

X

Index register low byte

 

 

 

 

 

 

I

Interrupt mask

 

 

Z

Zero bit

 

 

 

 

 

 

 

 

 

 

 

 

 

ii

Immediate operand byte

 

 

&

Logical AND

 

 

 

 

 

 

 

 

 

 

 

IMD

Immediate source to direct destination addressing mode

 

Logical OR

 

 

 

 

 

 

 

 

 

 

 

IMM

Immediate addressing mode

 

 

Logical EXCLUSIVE OR

 

 

 

 

INH

Inherent addressing mode

 

 

( )

Contents of

 

 

 

 

 

 

 

 

 

 

 

IX

Indexed, no offset addressing mode

 

 

–( )

Negation (two’s complement)

 

 

 

IX+

Indexed, no offset, post increment addressing mode

 

#

Immediate value

 

 

 

 

 

 

 

 

IX+D

Indexed with post increment to direct addressing mode

 

«

Sign extend

 

 

 

 

 

 

 

 

 

 

 

IX1

Indexed, 8-bit offset addressing mode

 

 

Loaded with

 

 

 

 

 

 

 

 

 

 

 

IX1+

Indexed, 8-bit offset, post increment addressing mode

 

?

If

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IX2

Indexed, 16-bit offset addressing mode

 

 

:

Concatenated with

 

 

 

 

 

 

 

 

M

Memory location

 

 



Set or cleared

 

 

 

 

 

 

 

 

 

 

N

Negative bit

 

 

Not affected

 

 

 

 

 

 

 

 

 

 

 

7.8 Opcode Map

See Table 7-2.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

89

Page 89
Image 89
Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Opcode Map, Instruction Set Summary Sheet 6

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.