Instruction Set Summary

Table 7-1. Instruction Set Summary (Sheet 4 of 6)

Source

Operation

 

 

 

 

 

 

 

Description

Form

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JMP opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JMP opr

 

 

PC ← Jump Address

JMP opr,X

Jump

 

JMP opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JMP ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JSR opr

 

PC ← (PC) + n (n = 1, 2, or 3)

JSR opr

 

 

Push (PCL); SP ← (SP) – 1

JSR opr,X

Jump to Subroutine

Push (PCH); SP ← (SP) – 1

JSR opr,X

 

 

PC ← Unconditional Address

JSR ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA #opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA opr,X

Load A from M

 

 

 

 

 

 

 

 

 

 

 

 

A ← (M)

LDA opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDA opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDHX #opr

Load H:X from M

 

 

 

 

 

H:X ← (M:M + 1)

LDHX opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX #opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX opr,X

Load X from M

 

 

 

 

 

 

 

 

 

 

 

 

X ← (M)

LDX opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LDX opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSL opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSLA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSLX

Logical Shift Left

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

LSL opr,X

(Same as ASL)

 

 

 

 

 

b7

 

 

 

 

 

 

 

 

 

 

 

 

 

b0

LSL ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSL opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSR opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSRA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSRX

Logical Shift Right

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

LSR opr,X

 

 

 

b7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b0

LSR ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSR opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOV opr,opr

 

(M)Destination ← (M)Source

MOV opr,X+

Move

MOV #opr,opr

H:X ← (H:X) + 1 (IX+D, DIX+)

 

MOV X+,opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MUL

Unsigned multiply

 

 

 

 

 

 

X:A ← (X) ⋅ (A)

NEG opr

 

 

M ← –(M) = $00 – (M)

NEGA

 

 

 

 

A ← –(A) = $00 – (A)

NEGX

 

 

Negate (Two’s Complement)

 

X ← –(X) = $00 – (X)

NEG opr,X

 

 

 

M ← –(M) = $00 – (M)

NEG ,X

 

 

 

 

M ← –(M) = $00 – (M)

NEG opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP

No Operation

 

 

 

 

 

 

 

 

 

 

 

 

None

NSA

Nibble Swap A

 

 

 

A ← (A[3:0]:A[7:4])

ORA #opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORA opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORA opr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORA opr,X

Inclusive OR A and M

 

 

 

 

 

 

 

 

A ← (A) (M)

ORA opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORA ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORA opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORA opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSHA

Push A onto Stack

Push (A); SP ← (SP) – 1

PSHH

Push H onto Stack

Push (H); SP ← (SP) – 1

PSHX

Push X onto Stack

Push (X); SP ← (SP) – 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Effect

Address Mode

on CCR

 

V H I N Z C

 

 

DIR

 

EXT

–– – – – – IX2 IX1

IX

DIR

EXT

–– – – – – IX2 IX1

IX

IMM

DIR

EXT 0 – –   – IX2IX1

IX

SP1

SP2

0 – –   – IMMDIR

IMM

DIR

EXT 0 – –   – IX2IX1

IX

SP1

SP2

DIR

INH

– –    INHIX1

IX SP1

DIR

INH

– – 0   INHIX1

IX SP1

DD 0 – –   – DIX+IMD IX+D

– 0 – – – 0 INH

DIR

INH

– –    INHIX1

IX SP1

– – – – – – INH

– – – – – – INH

IMM

DIR

EXT 0 – –   – IX2IX1

IX

SP1

SP2

– – – – – – INH

– – – – – – INH

– – – – – – INH

Opcode

Operand

Cycles

BC

dd

2

CC

hh ll

3

DC

ee ff

4

EC

ff

3

FC

 

2

BD

dd

4

CD

hh ll

5

DD

ee ff

6

ED

ff

5

FD

 

4

A6

ii

2

B6

dd

3

C6

hh ll

4

D6

ee ff

4

E6

ff

3

F6

 

2

9EE6

ff

4

9ED6

ee ff

5

45

ii jj

3

55

dd

4

AE

ii

2

BE

dd

3

CE

hh ll

4

DE

ee ff

4

EE

ff

3

FE

 

2

9EEE

ff

4

9EDE

ee ff

5

38

dd

4

48

 

1

58

 

1

68

ff

4

78

 

3

9E68

ff

5

34

dd

4

44

 

1

54

 

1

64

ff

4

74

 

3

9E64

ff

5

4E

dd dd

5

5E

dd

4

6E

ii dd

4

7E

dd

4

42

 

5

30

dd

4

40

 

1

50

 

1

60

ff

4

70

 

3

9E60

ff

5

9D

 

1

62

 

3

AA

ii

2

BA

dd

3

CA

hh ll

4

DA

ee ff

4

EA

ff

3

FA

 

2

9EEA

ff

4

9EDA

ee ff

5

87

 

2

8B

 

2

89

 

2

 

 

 

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

87

Page 86 Page 88
Page 87
Image 87
Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Instruction Set Summary Sheet 4, Jmp ,X
Page 86 Page 88

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.
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