Development Support

Features include:

Normal user-mode pin functionality

One pin dedicated to serial communication between monitor ROM and host computer

Standard mark/space non-return-to-zero (NRZ) communication with host computer

4800 baud–28.8 Kbaud communication with host computer

Execution of code in random-access memory (RAM) or ROM

FLASH programming

18.3.1 Functional Description

The monitor ROM receives and executes commands from a host computer. Figure 18-8shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface.

Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor.

18.3.1.1 Entering Monitor Mode

There are two methods for entering monitor:

The first is the traditional M68HC08 method where VDD + VHI is applied to IRQ1 and the mode pins are configured appropriately.

A second method, intended for in-circuit programming applications, will force entry into monitor mode without requiring high voltage on the IRQ1 pin when the reset vector locations of the FLASH are erased ($FF).

NOTE

For both methods, holding the PTC2 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50 percent duty cycle at maximum bus frequency.

Table 18-1is a summary of the differences between user mode and monitor mode.

Table 18-1. Mode Differences

 

 

 

Functions

 

 

 

 

 

 

 

Modes

 

 

 

 

 

 

 

 

 

 

 

COP

Rest

Reset

 

Break

Break

SWI

SWI

 

Vector High

Vector Low

 

Vector High

Vector Low

Vector High

Vector Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

User

Enabled

$FFFE

$FFFF

 

$FFFC

$FFFD

$FFFC

$FFFD

 

 

 

 

 

 

 

 

 

 

 

 

Monitor

Disabled(1)

$FEFE

$FEFF

 

$FEFC

$FEFD

$FEFC

$FEFD

 

 

 

 

 

 

 

 

 

 

 

 

1.If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register.

18.3.1.2 Normal Monitor Mode

Table 18-2shows the pin conditions for entering monitor mode.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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Freescale Semiconductor

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Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Entering Monitor Mode, Mode Differences, Normal Monitor Mode

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

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The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

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