I/O Registers

IDLE — Receiver Idle Bit

This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the

IDLE bit.

1 = Receiver input idle

0 = Receiver input active or idle since the IDLE bit was cleared

OR — Receiver Overrun Bit

This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit.

1 = Receive shift register full and SCRF = 1 0 = No receiver overrun

Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 13-12shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.

 

 

 

 

 

NORMAL FLAG CLEARING SEQUENCE

 

 

 

 

 

 

 

SCRF = 1

SCRF = 0

SCRF = 1

 

 

 

 

SCRF = 0

SCRF = 1

SCRF = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BYTE 1

BYTE 2

 

 

 

 

 

 

 

BYTE 3

 

 

 

 

 

BYTE 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ SCS1

 

 

READ SCS1

 

 

 

 

READ SCS1

 

 

 

 

 

 

 

 

SCRF = 1

 

 

 

 

SCRF = 1

 

 

 

 

 

 

SCRF = 1

 

 

 

 

 

OR = 0

 

 

 

OR = 0

 

 

 

OR = 0

 

 

READ SCDR

 

 

READ SCDR

 

 

READ SCDR

 

 

 

BYTE 1

 

 

 

 

BYTE 2

 

 

 

BYTE 3

 

 

 

 

 

 

 

 

DELAYED FLAG CLEARING SEQUENCE

 

 

 

 

 

 

 

SCRF = 1

 

 

SCRF = 1 OR = 1

SCRF = 0 OR = 1

SCRF = 1 OR = 1

SCRF = 0 OR = 0

BYTE 1

 

BYTE 2

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 1

BYTE 3

 

BYTE 4

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 3

Figure 13-12. Flag Clearing Sequence

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

175

Page 175
Image 175
Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Idle Receiver Idle Bit, Or Receiver Overrun Bit

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

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