Transmitter | Freescale Semiconductor MC68HC908MR16, MC68HC908MR32

Functional Description

13.3.2 Transmitter

Figure 13-5shows the structure of the SCI transmitter.

INTERNAL BUS

	⎟ 4	PRE-	BAUD	⎟ 16	SCI DATA REGISTER
		SCALER	DIVIDER

fOP

SCP1

SCP0

SCR2

SCR1

SCR0

TRANSMITTER CPU

INTERRUPT REQUEST

TXINV

PEN

PTY

STOP

11-BIT

START

TRANSMIT

SHIFT REGISTER

H

8

7

6

5

4

3

2

1

0

L

MSB

M

FROMLOADSCDR

PARITY

ENABLESHIFT

GENERATION

PREAMBLE 1sALL

BREAK 0sALL

T8

TRANSMITTER

CONTROL LOGIC

SCTE

SBK

SCTE

LOOPS

SCTIE

SCTIE

ENSCI

TC

TC

TE

TCIE

TCIE

PTF5/TxD

Figure 13-5. SCI Transmitter

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

161

Image 161

Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual SCI Transmitter

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.

Contents

MC68HC908MR32 MC68HC908MR16 Page MC68HC908MR32 MC68HC908MR16 Data SheetMC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Date Revision Description Level Numbers Revision HistoryRevision History List of Chapters List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Table of Contents Chapter Clock Generator Module CGM Table of ContentsChapter Analog-to-Digital Converter ADC Chapter Computer Operating Properly COP Chapter Configuration Register Config Chapter Low-Voltage Inhibit LVI Chapter Central Processor Unit CPUChapter External Interrupt IRQ Chapter Pulse-Width Modulator for Motor Control Pwmmc Chapter Power-On Reset PORChapter Input/Output I/O Ports Ports Chapter Serial Communications Interface Module SCI Chapter Serial Peripheral Interface Module SPI Chapter System Integration Module SIM Chapter Timer Interface a Tima Chapter Development Support Chapter Timer Interface B Timb Chapter Ordering Information and Mechanical Specifications Chapter Electrical Specifications Introduction FeaturesChapter General Description General Description MCU Block Diagram MCU Block Diagram Pin QFP Pin Assignments Pin Assignments Pin Assignments Pin Sdip Pin Assignments Oscillator Pins OSC1 and OSC2 Power Supply Pins VDD and VSSExternal Reset Pin RST CGM Power Supply Pins Vdda and Vssad Port a Input/Output I/O Pins PTA7-PTA0 Analog Power Supply Pins Vddad and VssadPort B I/O Pins PTB7/ATD7-PTB0/ATD0 Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8 PWM Ground Pin Pwmgnd Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK Reserved Memory Locations Chapter MemoryUnimplemented Memory Locations Memory I/O SectionMemory Map Memory Map MC68HC908MR32 Memory Map Memory Addr Control, Status, and Data Registers Summary Sheet 1 Memory Map Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 2 Memory Addr Register Name Control, Status, and Data Registers Summary Sheet 3 Control, Status, and Data Registers Summary Sheet 4 Memory Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 5 Addr Register Name Control, Status, and Data Registers Summary Sheet 6 Control, Status, and Data Registers Summary Sheet 7 Control, Status, and Data Registers Summary Sheet 8 Address Vector Low Vector Addresses Monitor ROM Random-Access Memory RAMMonitor ROM Address Vector Flash Control Register Flash Memory Flash Flash Page Erase Operation Hven High-Voltage Enable BitMass Mass Erase Control Bit Erase Erase Control Bit Flash Mass Erase Operation Only bytes which are currently $FF may be programmed Flash Program Operation Flash Programming Flowchart Flash Block Protect Register Flash Block Protection Examples of Protect Start Address Wait ModeStop Mode Functional Description Chapter Analog-to-Digital Converter ADC Analog-to-Digital Converter ADC Block Diagram Highlighting ADC Block and Pins Functional Description ADC Port I/O PinsVoltage Conversion Result Justification Conversion TimeContinuous Conversion Monotonicity Bit Truncation Mode Error Interrupts Wait ModeI/O Signals ADC Voltage In Advin I/O RegistersADC External Connections 6.2 ANx ADC Status and Control Register Aien ADC Interrupt Enable Bit Input Select Mux Channel Select ADC Data Register Low ADC Data Register High ADC Clock Rate ADC Clock RegisterADC Clock Divide Ratio Analog-to-Digital Converter ADC Cgmvclk Chapter Clock Generator Module CGM Clock Generator Module CGM CGM Block Diagram PLL Circuits Phase-Locked Loop Circuit PLLCrystal Oscillator Circuit Manual and Automatic PLL Bandwidth Modes Acquisition and Tracking Modes Variable Definition Programming the PLLVariable Definitions Special Programming Exceptions Base Clock Selector Circuit CGM External Connections CGM External Connections Oscillator Enable Signal Simoscen PLL Analog Power Pin VddaCrystal Amplifier Input Pin OSC1 Crystal Amplifier Output Pin OSC2 CGM Registers Crystal Output Frequency Signal CgmxclkCGM Base Clock Output Cgmout CGM CPU Interrupt Cgmint Pllf PLL Interrupt Flag PLL Control RegisterPllon PLL On Bit BCS Base Clock Select Bit ACQ Acquisition Mode Bit Lock Lock Indicator BitPLL Bandwidth Control Register PCTL30 Unimplemented Bits XLD Crystal Loss Detect Bit PLL Programming RegisterPBWC30 Reserved for Test VCO Frequency Multiplier N Selection Interrupts VRS74 VCO Range Select Bits Parametric Influences on Reaction Time Acquisition/Lock Time SpecificationsAcquisition/Lock Time Definitions Reaction Time Calculation Acquisition/Lock Time SpecificationsChoosing a Filter Capacitor Frequency Chapter Configuration Register Config Configuration Register Chapter Computer Operating Properly COP COP Block Diagram Internal Reset Power-On ResetReset Vector Fetch Copctl Write Stop Mode Monitor ModeCopd COP Disable COP Control Register Freescale Semiconductor CPU Registers Chapter Central Processor Unit CPU Central Processor Unit CPU AccumulatorIndex Register CPU Registers Stack PointerProgram Counter Half-Carry Flag Condition Code RegisterInterrupt Mask Negative Flag Arithmetic/Logic Unit ALU Low-Power ModesCPU During Break Interrupts Zero Flag Instruction Set Summary Sheet 1 Instruction Set Summary Source Operation Description On CCR Form Instruction Set Summary Sheet 2Instruction Set Summary Dbnz opr,rel Instruction Set Summary Sheet 3 JMP ,X Instruction Set Summary Sheet 4 Operation Description On CCR Form Instruction Set Summary Sheet 5 Opcode Map Opcode MapInstruction Set Summary Sheet 6 9ED 9EE Opcode Map Chapter External Interrupt IRQ IRQ Module Block Diagram External Interrupt IRQ IRQ Pin IRQ Pin IRQ Interrupt Flowchart IRQ Status and Control Register Iscr IRQ Status and Control Register IRQ Status and Control Register Irqf IRQ Flag Freescale Semiconductor Chapter Low-Voltage Inhibit LVI LVI Module Block Diagram False Reset Protection Forced Reset OperationPolled LVI Operation LVI Trip Selection LVI Interrupts LVI Status and Control RegisterLviout Bit Indication LVI Status and Control Register 100 Freescale Semiconductor I/O Port Register Summary Chapter Input/Output I/O Ports Ports Input/Output I/O Ports Ports Addr Register Name Port a Data Register Port aData Direction Register a Port a Port B Data Register Port BPort a Pin Functions Input/Output I/O Ports Ports Port B Data Direction Register BPort B Pin Functions Data Direction Register C Port CPort C Data Register Port C Pin Functions Port DPort D PTC60 Port E PTD Bit Pin Mode Accesses to PTD ReadPort E Data Register Port D Pin Functions Data Direction Register E Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTEPort E Pin Functions Port E Data Direction Register F Port FPort F Data Register Port F Port F Pin Functions 112 Freescale Semiconductor Chapter Power-On Reset POR 114 Freescale Semiconductor Chapter Pulse-Width Modulator for Motor Control Pwmmc Pulse-Width Modulator for Motor Control Pwmmc Block Diagram Highlighting Pwmmc Block and Pins Features PWM Module Block Diagram Register Summary Sheet 2 Register Summary Sheet 3 Features Addr Register Name Bit Timebase Resolution Timebase Edge-Aligned PWM Positive Polarity Prescaler PWM GeneratorsLoad Operation PWM Prescaler PWM Interrupt Requests Reload Frequency Change Center-Aligned PWM Value Loading PWMVALxHPWMVALxL Condition PWM Value Used PWM Data Overflow and Underflow ConditionsPWM Data Overflow and Underflow Conditions Output Control 12. Complementary Pairing Output Control Dead-Time Insertion 14. Dead-Time Generators 15. Effects of Dead-Time Insertion 17. Dead-Time and Small Pulse Widths Current Voltage On Current Current Sense Pins Current Correction Bits Correction Method ISENS1 and ISENS0 Correction Methods 20. Top/Bottom Correction for PWMs 1 Output Polarity 21. PWM Polarity OUTx Bits OUTx Bit Complementary Mode Independent ModePWM Output Port Control 23. Dead-Time Insertion During Outctl = Fault Protection Fault ProtectionFault Condition Input Pins 26. PWM Disabling Scheme Automatic Mode Fault Pin Filter Manual Mode 28. PWM Disabling in Automatic Mode Output Port Control Software Output Disable Initialization and the Pwmen Bit 32. Pwmen and PWM Pins PWM Operation in Wait Mode PWM Operation in Wait ModeControl Logic Block PWM Counter Registers 35. PWM Counter Modulo Register High Pmodh PWM Counter Modulo Registers Control Logic Block PWMx Value Registers Pwmint PWM Interrupt Enable Bit Disy Software Disable Bit for Bank Y BitPWM Control Register Pwmf PWM Reload Flag LDOK- Load OK Bit Pwmen PWM Module Enable Bit IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1 PRSC1 and PRSC0 PWM Prescaler Bits IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5 Dead-Time Write-Once Register PWM Disable Mapping Write-Once RegisterFault Control Register FINT1 Fault 1 Interrupt Enable Bit FINT3 Fault 3 Interrupt Enable BitFINT2 Fault 2 Interrupt Enable Bit Fault Status Register Fault Acknowledge Register DT2 Dead-Time 2 Bit PWM Output Control RegisterDT1 Dead-Time 1 Bit 10. OUTx Bits PWM Glossary PWM Glossary 48. PWM Load Cycle/Frequency Definition Chapter Serial Communications Interface Module SCI Serial Communications Interface Module SCI Block Diagram Highlighting SCI Block and Pins SCI Module Block Diagram Serial Communications Interface Module SCI Addr Data Format SCI Transmitter Transmitter Break Characters Character LengthCharacter Transmission Idle Characters ReceiverInversion of Transmitted Output Transmitter Interrupts SCI Receiver Block Diagram Data Sampling Character Reception Start Bit Verification Data Bit RecoveryStop Bit Recovery Error Interrupts Framing ErrorsReceiver Wakeup Receiver Interrupts 13.6.1 PTF5/TxD Transmit Data 13.6 I/O SignalsSCI During Break Module Interrupts SCI Control Register 13.7 I/O Registers13.6.2 PTF4/RxD Receive Data Mode Character Length Bit Ensci Enable SCI BitPEN Parity Enable Bit Txinv Transmit Inversion Bit Character Format Selection Tcie Transmission Complete Interrupt Enable BitControl Bits Character Format Start Data Parity Stop Ilie Idle Line Interrupt Enable Bit Scrie SCI Receive Interrupt Enable BitTE Transmitter Enable Bit RE Receiver Enable Bit Neie Receiver Noise Error Interrupt Enable Bit Orie Receiver Overrun Interrupt Enable BitFeie Receiver Framing Error Interrupt Enable Bit Peie Receiver Parity Error Interrupt Enable Bit Scrf SCI Receiver Full Bit SCI Status RegisterTC Transmission Complete Bit Or Receiver Overrun Bit Idle Receiver Idle Bit NF Receiver Noise Flag Bit FE Receiver Framing Error BitPE Receiver Parity Error Bit SCI Baud Rate Register SCI Data RegisterRPF -Reception-in-Progress Flag SCI Baud Rate Prescaling Baud Rate Divisor BD SCI Baud Rate Selection Baud Rate Divisor PD Divisor BD SCI Baud Rate Selection Examples 180 Freescale Semiconductor Chapter System Integration Module SIM Signal Name ConventionsSignal Name Description SIM Bus Clock Control and Generation Clock Startup from POR or LVI ResetBus Timing System Integration Module SIM Clocks in Wait Mode Reset and System InitializationExternal Pin Reset Reset and System Initialization PIN Bit Set Timing Active Resets from Internal SourcesReset Type Number of Cycles Required to Set PIN Computer Operating Properly COP Reset Power-On Reset POR SIM Counter SIM Counter During Power-On ResetSIM Counter and Reset States Exception Control Exception ControlInterrupts Interrupt Processing Hardware Interrupts Interrupt Recovery Software Interrupt SWI Instruction Low-Power ModeReset SIM Registers SIM RegistersSIM Break Status Register PIN External Reset Bit SIM Reset Status RegisterIlop Illegal Opcode Reset Bit Ilad Illegal Address Reset Bit opcode fetches only SIM Break Flag Control Register 194 Freescale Semiconductor Pin Name Conventions Chapter Serial Peripheral Interface Module SPIPin Name Conventions Serial Peripheral Interface Module SPI Block Diagram Highlighting SPI Block and Pins SPI Module Block Diagram Serial Peripheral Interface Module SPI Addr Master Mode Clock Phase and Polarity Controls Slave ModeTransmission Formats Transmission Formats Transmission Format Cpha = Transmission Format When Cpha = Transmission Initiation Latency Transmission Start Delay Master Error Conditions Error ConditionsOverflow Error 10. Clearing Sprf When Ovrf Interrupt Is Not Enabled Mode Fault Error Freescale Semiconductor 205 Flag Request SPI Interrupts Queuing Transmission Data Resetting the SPIResetting the SPI 12. SPRF/SPTE CPU Interrupt Timing 15.11 I/O Signals Miso Master In/Slave Out SignalsMosi Master Out/Slave Spsck Serial Clock SPI Configuration State of SS Logic SPI Configuration15.12 I/O Registers VSS Clock Ground Spwom SPI Wired-OR Mode Bit Cpha Clock Phase BitSpmstr SPI Master Bit Cpol Clock Polarity Bit SPTIE- SPI Transmit Interrupt Enable Bit SPE SPI Enable BitErrie Error Interrupt Enable Bit SPI Status and Control Register Modfen Mode Fault Enable Bit Modf Mode Fault BitOvrf Overflow Bit Spte SPI Transmitter Empty Bit SPI Master Baud Rate Selection SPI Data Register 2is a block diagram of the Tima Chapter Timer Interface a Tima Timer Interface a Tima Block Diagram Highlighting Tima Block and Pins Tima Block Diagram TIM I/O Register Summary Timer Interface a Tima Addr Register Name Bit Input Capture Tima Counter Prescaler Unbuffered Output Compare Output Compare Buffered Output Compare Pulse-Width Modulation PWM PWM Period and Pulse Width Unbuffered PWM Signal Generation PWM Initialization Buffered PWM Signal Generation 224 Freescale Semiconductor Tima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A 16.6 I/O Signals16.7 I/O Registers Tima Clock Pin PTE3/TCLKA Tstop Tima Stop Bit Toie Tima Overflow Interrupt Enable BitTrst Tima Reset Bit PS20 Prescaler Select Bits Tima Counter RegistersPrescaler Selection PS20 Tima Clock Source Tima Channel Status and Control Registers Tima Counter Modulo Registers CHxIE Channel x Interrupt Enable Bit ELSxB and ELSxA Edge/Level Select Bits MSxB Mode Select Bit BMSxA Mode Select Bit a Mode, Edge, and Level Selection MSxBMSxA ELSxBELSxA Mode ConfigurationTOVx Toggle-On-Overflow Bit CHxMAX Channel x Maximum Duty Cycle Bit 10. Tima Channel Registers Tima Channel Registers 10. Tima Channel Registers TACH0H/L-TACH3H/L 234 Freescale Semiconductor Timb module is not available in the 56-pin Sdip Chapter Timer Interface B Timb Timer Interface B Timb Block Diagram Highlighting Timb Block and Pins Timb Block Diagram Timb Counter Prescaler Timer Interface B Timb Addr Register Name Bit Freescale Semiconductor 239 240 Freescale Semiconductor Freescale Semiconductor 241 242 Freescale Semiconductor Timb Clock Pin PTE0/TCLKB 17.6 I/O SignalsTimb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1B Timb Status and Control Register Toie Timb Overflow Interrupt Enable Bit17.7 I/O Registers PS20 Timb Clock Source Trst Timb Reset BitTstop Timb Stop Bit Timb Counter Modulo Registers Timb Counter Registers Timb Channel Status and Control Registers 248 Freescale Semiconductor PWM 10. Timb Channel Registers TBCH0H/L-TBCH1H/L Timb Channel Registers Break Module BRK Chapter Development SupportFunctional Description Flag Protection During Break Interrupts Development Support Break Module Block Diagram Break Module Registers Low-Power Modes Break Address Registers Break Status and Control RegisterBrka Break Active Bit Break Status Register Monitor ROM MONBreak Flag Control Register Monitor ROM MON Normal Monitor Mode Entering Monitor ModeMode Differences Monitor Mode Circuit $FFFF Monitor Mode Signal Requirements and Options Data Format Forced Monitor Mode Echoing Break SignalCommands Write Write Memory Command Read Read Memory CommandIread Indexed Read Command Command Sequence RUN Run User Program Command Iwrite Indexed Write CommandReadsp Read Stack Pointer Command Monitor Baud Rate Selection SecurityBaud Rate 13. Monitor Mode Entry Timing Absolute Maximum Ratings Chapter Electrical SpecificationsCharacteristic1 Symbol Value Unit Electrical Specifications Thermal CharacteristicsCharacteristic Symbol Value Unit Functional Operating Range Characteristic1 Symbol Min Typ2 Max Unit DC Electrical CharacteristicsDC Electrical Characteristics Characteristic Symbol Min Typ Max Unit Flash Memory CharacteristicsCharacteristic Symbol Min Max Unit Control Timing Diagram Characteristic2 Symbol Min Max Unit Number1 Serial Peripheral Interface CharacteristicsSerial Peripheral Interface Characteristics SPI Master Timing SPI Slave Timing Clock Generation Module Component Specifications TImer Interface Module CharacteristicsCharacteristic Symbol Min Typ Max CGM Operating Conditions Description Symbol Min Typ Max CGM Acquisition/Lock Time SpecificationsCGM Acquisition/Lock Time Specifications 3FF Analog-to-Digital Converter ADC Characteristics Order Numbers Chapter Ordering Information and Mechanical SpecificationsOrder Numbers MC Order Number Operating 20.3 64-Pin Plastic Quad Flat Pack QFP Ordering Information and Mechanical Specifications Pin Shrink Dual In-Line Package Sdip 20.4 56-Pin Shrink Dual In-Line Package Sdip 278 Freescale Semiconductor Appendix a MC68HC908MR16 MC68HC908MR16 Figure A-1. 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