Freescale Semiconductor MC68HC908MR32 manual SIM Bus Clock Control and Generation, Bus Timing

System Integration Module (SIM)

WAIT

CONTROL

SIM

COUNTER

⎟ 2

CLOCK	CLOCK GENERATORS
CONTROL

MODULE WAIT

CPU WAIT (FROM CPU)

SIMOSCEN (TO CGM)

COP CLOCK

CGMXCLK (FROM CGM)

CGMOUT (FROM CGM)

INTERNAL CLOCKS

RESET

PIN LOGIC

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

RESET

MASTER

RESET

CONTROL

LVI (FROM LVI MODULE)

ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS)

COP (FROM COP MODULE)

INTERRUPT CONTROL INTERRUPT SOURCES

AND PRIORITY DECODE

CPU INTERFACE

Figure 14-1. SIM Block Diagram

14.2 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-2. This clock can come from either an external oscillator or from the on-chip phase-locked loop (PLL) circuit. See Chapter 4 Clock Generator Module (CGM).

14.2.1 Bus Timing

In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. See Chapter 4 Clock Generator Module (CGM).

14.2.2 Clock Startup from POR or LVI Reset

When the power-on reset (POR) module or the low-voltage inhibit (LVI) module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The internal bus (IBUS) clocks start upon completion of the timeout.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

182 Freescale Semiconductor