Freescale Semiconductor MC68HC908MR32 manual CGM Block Diagram, Clock Generator Module CGM

Clock Generator Module (CGM)

CRYSTAL OSCILLATOR

OSC2
							CGMXCLK
							TO SIM
OSC1				CLOCK	⎟ 2	A	CGMOUT
				SELECT		B	TO SIM
				CIRCUIT			S*
SIMOSCEN							*WHEN S = 1, CGMOUT = B
CGMRDV	CGMRCLK			BCS
	VDDA	CGMXFC		VSS			USER MODE
				VRS[7:4]			PTC2
							MONITOR MODE
PHASE		LOOP		VOLTAGE
				CONTROLLED
DETECTOR		FILTER
				OSCILLATOR
				PLL ANALOG
LOCK		BANDWIDTH		INTERRUPT			CGMINT
DETECTOR		CONTROL		CONTROL
LOCK		AUTO	ACQ	PLLIE	PLLF
		MUL[7:4]
CGMVDV		FREQUENCY		CGMVCLK
		DIVIDER

Figure 4-1. CGM Block Diagram

Addr.	Register Name		Bit 7	6	5		4	3	2	1	Bit 0
	PLL Control Register	Read:	PLLIE	PLLF	PLLON		BCS	1	1	1	1
$005C	(PCTL)	Write:		R				R	R	R	R
	See page 66.
		Reset:	0	0	1		0	1	1	1	1
	PLL Bandwidth Control Register	Read:		LOCK			XLD	0	0	0	0
			AUTO			ACQ
$005D	(PBWC)	Write:		R				R	R	R	R
	See page 67.
		Reset:	0	0	0		0	0	0	0	0
	PLL Programming Register	Read:
			MUL7	MUL6	MUL5		MUL4	VRS7	VRS6	VRS5	VRS4
$005E	(PPG)	Write:
	See page 68.
		Reset:	0	1	1		0	0	1	1	0
			R	= Reserved

Figure 4-2. CGM I/O Register Summary

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

58 Freescale Semiconductor