Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 Flash Memory Characteristics, Control Timing

Electrical Specifications

19.6 FLASH Memory Characteristics

Characteristic	Symbol	Min	Typ	Max	Unit
RAM data retention voltage	VRDR	1.3	—	—	V
FLASH program bus clock frequency	—	1	—	—	MHz
FLASH read bus clock frequency	(1)	0	—	8 M	Hz
	fRead
FLASH page erase time	tErase
<1 K cycles		0.9	1	1.1	ms
>1 K cycles		3.6	4	5.5
FLASH mass erase time	tMErase	4	—	—	ms
FLASH PGM/ERASE to HVEN setup time	tNVS	10	—	—	∝s
FLASH high-voltage hold time	tNVH	5	—	—	∝s
FLASH high-voltage hold time (mass erase)	tNVHL	100	—	—	∝s
FLASH program hold time	tPGS	5	—	—	∝s
FLASH program time	tPROG	30	—	40	∝s
FLASH return to read time	(2)	1	—	—	∝s
	tRCV
FLASH cumulative program HV period	(3)	—	—	4	ms
	tHV
FLASH endurance(4)	—	10 k	100 k	—	Cycles
FLASH data retention time(5)	—	15	100	—	Years

1.fRead is defined as the frequency range for which the FLASH memory can be read.

2.tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to 0.

3.tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum.

4.Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619.

5.Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618.

19.7 Control Timing

	Characteristic(1)	Symbol	Min	Max	Unit
Frequency of operation(2)		fOSC	1
Crystal option				8	MHz
External clock option(3)			dc(4)	32.8
Internal operating frequency		fOP	—	8.2	MHz
	input pulse width low(5)	tIRL	50	—	ns
RESET

1.VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted

2.See 19.8 Serial Peripheral Interface Characteristics for more information.

3.No more than 10% duty cycle deviation from 50%.

4.Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information.

5.Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

268 Freescale Semiconductor