Chapter 9

Low-Voltage Inhibit (LVI)

9.1 Introduction

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage.

9.2 Features

Features of the LVI module include:

Programmable LVI reset

Programmable power consumption

Digital filtering of VDD pin level

Selectable LVI trip voltage

9.3 Functional Description

Figure 9-1shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD falls below a voltage, VLVRX, and remains at or below that level for nine or more consecutive CGMXCLK.

VLVRX and VLVHX are determined by the TRPSEL bit in the LVISCR (see Figure 9-2). LVIPWR and LVIRST are in the configuration register (CONFIG). See Chapter 5 Configuration Register (CONFIG).

VDD

LOW VDD

DETECTOR

TRPSEL

FROM LVISCR

LVIPWR

FROM CONFIG

CPU CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

VDD > LVItrip = 0

 

 

 

 

 

 

DIGITAL FILTER

VDD < LVItrip = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ANLGTRIP

 

 

 

 

 

 

 

 

 

FROM CONFIG

LVIRST

LVIOUT

LVI RESET

Figure 9-1. LVI Module Block Diagram

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

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Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Chapter Low-Voltage Inhibit LVI, LVI Module Block Diagram

MC68HC908MR16, MC68HC908MR32 specifications

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