Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Chapter Input/Output I/O Ports Ports

Chapter 10

Input/Output (I/O) Ports (PORTS)

10.1 Introduction

Thirty-seven bidirectional input-output (I/O) pins and seven input pins form six parallel ports. All I/O pins are programmable as inputs or outputs.

When using the 56-pin package version:

•Set the data direction register bits in DDRC such that bit 1 is written to a logic 1 (along with any other output bits on port C).

•Set the data direction register bits in DDRE such that bits 0, 1, and 2 are written to a logic 1 (along with any other output bits on port E).

•Set the data direction register bits in DDRF such that bits 0, 1, 2, and 3 are written to a logic 1 (along with any other output bits on port F).

NOTE

Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although PWM6–PWM1 do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.

Addr.	Register Name		Bit 7	6	5	4	3	2	1	Bit 0
	Port A Data Register	Read:	PTA7	PTA6	PTA5	PTA4	PTA3	PTA2	PTA1	PTA0
$0000	(PTA)	Write:
	See page 103.
		Reset:				Unaffected by reset
	Port B Data Register	Read:
			PTB7	PTB6	PTB5	PTB4	PTB3	PTB2	PTB1	PTB0
$0001	(PTB)	Write:
	See page 104.
		Reset:				Unaffected by reset
	Port C Data Register	Read:	0	PTC6	PTC5	PTC4	PTC3	PTC2	PTC1	PTC0
$0002	(PTC)	Write:	R
	See page 106.
		Reset:				Unaffected by reset
	Port D Data Register	Read:	0	PTD6	PTD5	PTD4	PTD3	PTD2	PTD1	PTD0
$0003	(PTD)	Write:	R	R	R	R	R	R	R	R
	See page 107.
		Reset:				Unaffected by reset
	Data Direction Register A	Read:
			DDRA7	DDRA6	DDRA5	DDRA4	DDRA3	DDRA2	DDRA1	DDRA0
$0004	(DDRA)	Write:
	See page 103.
		Reset:	0	0	0	0	0	0	0	0

R

= Reserved = Unimplemented

Figure 10-1. I/O Port Register Summary

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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