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Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual PWM Polarity

Models: MC68HC908MR16 MC68HC908MR32

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Pulse-Width Modulator for Motor Control (PWMMC)

CENTER-ALIGNED POSITIVE POLARITY

UP/DOWN COUNTER

MODULUS = 4

PWM <= 0

PWM = 1

PWM = 2

PWM = 3

PWM >= 4

CENTER-ALIGNED NEGATIVE POLARITY

UP/DOWN COUNTER

MODULUS = 4

PWM <= 0

PWM = 1

PWM = 2

PWM = 3

PWM >= 4

EDGE-ALIGNED POSITIVE POLARITY

UP-ONLY COUNTER

MODULUS = 4

PWM <= 0

PWM = 1

PWM = 2

PWM = 3

PWM >= 4

EDGE-ALIGNED NEGATIVE POLARITY

UP-ONLY COUNTER

MODULUS = 4

PWM <= 0

PWM = 1

PWM = 2

PWM = 3

PWM >= 4

Figure 12-21. PWM Polarity

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

134	Freescale Semiconductor

Image 134

Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual PWM Polarity

Contents

MC68HC908MR32 MC68HC908MR16 Page MC68HC908MR32 MC68HC908MR16 Data SheetMC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Date Revision Description Level Numbers Revision HistoryRevision History List of Chapters List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Table of Contents Chapter Clock Generator Module CGM Table of ContentsChapter Analog-to-Digital Converter ADC Chapter Configuration Register Config Chapter Computer Operating Properly COPChapter Low-Voltage Inhibit LVI Chapter Central Processor Unit CPUChapter External Interrupt IRQ Chapter Pulse-Width Modulator for Motor Control Pwmmc Chapter Power-On Reset PORChapter Input/Output I/O Ports Ports Chapter Serial Communications Interface Module SCI Chapter System Integration Module SIM Chapter Serial Peripheral Interface Module SPIChapter Timer Interface a Tima Chapter Timer Interface B Timb Chapter Development SupportChapter Electrical Specifications Chapter Ordering Information and Mechanical SpecificationsIntroduction FeaturesChapter General Description MCU Block Diagram General DescriptionDiagram MCU BlockPin Assignments Pin QFP Pin AssignmentsPin Sdip Pin Assignments Pin AssignmentsExternal Reset Pin RST Power Supply Pins VDD and VSSOscillator Pins OSC1 and OSC2 CGM Power Supply Pins Vdda and VssadPort B I/O Pins PTB7/ATD7-PTB0/ATD0 Analog Power Supply Pins Vddad and VssadPort a Input/Output I/O Pins PTA7-PTA0 Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK PWM Ground Pin PwmgndReserved Memory Locations Chapter MemoryUnimplemented Memory Locations Memory I/O SectionMemory Map MC68HC908MR32 Memory Map Memory MapControl, Status, and Data Registers Summary Sheet 1 Memory AddrControl, Status, and Data Registers Summary Sheet 2 Memory Map Addr Register Name BitControl, Status, and Data Registers Summary Sheet 3 Memory Addr Register NameControl, Status, and Data Registers Summary Sheet 4 Control, Status, and Data Registers Summary Sheet 5 Memory Addr Register Name BitControl, Status, and Data Registers Summary Sheet 6 Addr Register NameControl, Status, and Data Registers Summary Sheet 7 Control, Status, and Data Registers Summary Sheet 8 Vector Addresses Address Vector LowMonitor ROM Random-Access Memory RAMMonitor ROM Address VectorFlash Memory Flash Flash Control RegisterMass Mass Erase Control Bit Hven High-Voltage Enable BitFlash Page Erase Operation Erase Erase Control BitFlash Mass Erase Operation Flash Program Operation Only bytes which are currently $FF may be programmedFlash Programming Flowchart Flash Block Protection Flash Block Protect RegisterExamples of Protect Start Address Wait ModeStop Mode Chapter Analog-to-Digital Converter ADC Functional DescriptionBlock Diagram Highlighting ADC Block and Pins Analog-to-Digital Converter ADCFunctional Description ADC Port I/O PinsVoltage Conversion Result Justification Conversion TimeContinuous Conversion Bit Truncation Mode Error MonotonicityInterrupts Wait ModeI/O Signals ADC External Connections I/O RegistersADC Voltage In Advin 6.2 ANxAien ADC Interrupt Enable Bit ADC Status and Control RegisterMux Channel Select Input SelectADC Data Register High ADC Data Register LowADC Clock Rate ADC Clock RegisterADC Clock Divide Ratio Analog-to-Digital Converter ADC Chapter Clock Generator Module CGM CgmvclkCGM Block Diagram Clock Generator Module CGMPLL Circuits Phase-Locked Loop Circuit PLLCrystal Oscillator Circuit Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth ModesVariable Definition Programming the PLLVariable Definitions Base Clock Selector Circuit Special Programming ExceptionsCGM External Connections CGM External ConnectionsCrystal Amplifier Input Pin OSC1 PLL Analog Power Pin VddaOscillator Enable Signal Simoscen Crystal Amplifier Output Pin OSC2CGM Base Clock Output Cgmout Crystal Output Frequency Signal CgmxclkCGM Registers CGM CPU Interrupt CgmintPllon PLL On Bit PLL Control RegisterPllf PLL Interrupt Flag BCS Base Clock Select BitPLL Bandwidth Control Register Lock Lock Indicator BitACQ Acquisition Mode Bit PCTL30 Unimplemented BitsPBWC30 Reserved for Test PLL Programming RegisterXLD Crystal Loss Detect Bit VCO Frequency Multiplier N SelectionVRS74 VCO Range Select Bits InterruptsParametric Influences on Reaction Time Acquisition/Lock Time SpecificationsAcquisition/Lock Time Definitions Reaction Time Calculation Acquisition/Lock Time SpecificationsChoosing a Filter Capacitor Frequency Chapter Configuration Register Config Configuration Register COP Block Diagram Chapter Computer Operating Properly COPReset Vector Fetch Power-On ResetInternal Reset Copctl WriteCopd COP Disable Monitor ModeStop Mode COP Control RegisterFreescale Semiconductor Chapter Central Processor Unit CPU CPU RegistersCentral Processor Unit CPU AccumulatorIndex Register CPU Registers Stack PointerProgram Counter Interrupt Mask Condition Code RegisterHalf-Carry Flag Negative FlagCPU During Break Interrupts Low-Power ModesArithmetic/Logic Unit ALU Zero FlagInstruction Set Summary Instruction Set Summary Sheet 1Source Operation Description On CCR Form Instruction Set Summary Sheet 2Instruction Set Summary Instruction Set Summary Sheet 3 Dbnz opr,relInstruction Set Summary Sheet 4 JMP ,XInstruction Set Summary Sheet 5 Operation Description On CCR FormOpcode Map Opcode MapInstruction Set Summary Sheet 6 Opcode Map 9ED 9EEIRQ Module Block Diagram Chapter External Interrupt IRQIRQ Pin External Interrupt IRQIRQ Interrupt Flowchart IRQ PinIRQ Status and Control Register IRQ Status and Control Register IscrIrqf IRQ Flag IRQ Status and Control RegisterFreescale Semiconductor LVI Module Block Diagram Chapter Low-Voltage Inhibit LVIPolled LVI Operation Forced Reset OperationFalse Reset Protection LVI Trip SelectionLviout Bit Indication LVI Status and Control RegisterLVI Interrupts LVI Status and Control Register100 Freescale Semiconductor Chapter Input/Output I/O Ports Ports I/O Port Register SummaryInput/Output I/O Ports Ports Addr Register Name Data Direction Register a Port aPort a Data Register Port aPort a Pin Functions Port BPort B Data Register Input/Output I/O Ports PortsPort B Data Direction Register BPort B Pin Functions Data Direction Register C Port CPort C Data Register Port D Port DPort C Pin Functions PTC60Port E Data Register PTD Bit Pin Mode Accesses to PTD ReadPort E Port D Pin FunctionsPort E Pin Functions Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTEData Direction Register E Port EData Direction Register F Port FPort F Data Register Port F Pin Functions Port F112 Freescale Semiconductor Chapter Power-On Reset POR 114 Freescale Semiconductor Chapter Pulse-Width Modulator for Motor Control Pwmmc Block Diagram Highlighting Pwmmc Block and Pins Pulse-Width Modulator for Motor Control PwmmcPWM Module Block Diagram FeaturesRegister Summary Sheet 2 Features Addr Register Name Bit Register Summary Sheet 3Resolution TimebaseEdge-Aligned PWM Positive Polarity TimebaseLoad Operation PWM GeneratorsPrescaler PWM PrescalerReload Frequency Change PWM Interrupt RequestsCenter-Aligned PWM Value Loading PWMVALxHPWMVALxL Condition PWM Value Used PWM Data Overflow and Underflow ConditionsPWM Data Overflow and Underflow Conditions 12. Complementary Pairing Output ControlDead-Time Insertion Output Control14. Dead-Time Generators 15. Effects of Dead-Time Insertion 17. Dead-Time and Small Pulse Widths Current Sense Pins Current Voltage On CurrentCorrection Methods Current Correction Bits Correction Method ISENS1 and ISENS0Output Polarity 20. Top/Bottom Correction for PWMs 121. PWM Polarity OUTx Bits OUTx Bit Complementary Mode Independent ModePWM Output Port Control 23. Dead-Time Insertion During Outctl = Fault Protection Fault ProtectionFault Condition Input Pins 26. PWM Disabling Scheme Fault Pin Filter Automatic Mode28. PWM Disabling in Automatic Mode Manual ModeSoftware Output Disable Output Port Control32. Pwmen and PWM Pins Initialization and the Pwmen BitControl Logic Block PWM Operation in Wait ModePWM Operation in Wait Mode PWM Counter RegistersPWM Counter Modulo Registers 35. PWM Counter Modulo Register High PmodhPWMx Value Registers Control Logic BlockPWM Control Register Disy Software Disable Bit for Bank Y BitPwmint PWM Interrupt Enable Bit Pwmf PWM Reload FlagPwmen PWM Module Enable Bit LDOK- Load OK BitIPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1 PRSC1 and PRSC0 PWM Prescaler Bits IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5 Dead-Time Write-Once Register PWM Disable Mapping Write-Once RegisterFault Control Register FINT1 Fault 1 Interrupt Enable Bit FINT3 Fault 3 Interrupt Enable BitFINT2 Fault 2 Interrupt Enable Bit Fault Status Register Fault Acknowledge Register DT1 Dead-Time 1 Bit PWM Output Control RegisterDT2 Dead-Time 2 Bit 10. OUTx BitsPWM Glossary PWM Glossary48. PWM Load Cycle/Frequency Definition Chapter Serial Communications Interface Module SCI Block Diagram Highlighting SCI Block and Pins Serial Communications Interface Module SCISCI Module Block Diagram Data Format Serial Communications Interface Module SCI AddrTransmitter SCI TransmitterBreak Characters Character LengthCharacter Transmission Inversion of Transmitted Output ReceiverIdle Characters Transmitter InterruptsSCI Receiver Block Diagram Character Reception Data SamplingStart Bit Verification Data Bit RecoveryStop Bit Recovery Receiver Wakeup Framing ErrorsError Interrupts Receiver Interrupts13.6.1 PTF5/TxD Transmit Data 13.6 I/O SignalsSCI During Break Module Interrupts SCI Control Register 13.7 I/O Registers13.6.2 PTF4/RxD Receive Data PEN Parity Enable Bit Ensci Enable SCI BitMode Character Length Bit Txinv Transmit Inversion BitControl Bits Character Format Tcie Transmission Complete Interrupt Enable BitCharacter Format Selection Start Data Parity StopTE Transmitter Enable Bit Scrie SCI Receive Interrupt Enable BitIlie Idle Line Interrupt Enable Bit RE Receiver Enable BitFeie Receiver Framing Error Interrupt Enable Bit Orie Receiver Overrun Interrupt Enable BitNeie Receiver Noise Error Interrupt Enable Bit Peie Receiver Parity Error Interrupt Enable BitScrf SCI Receiver Full Bit SCI Status RegisterTC Transmission Complete Bit Idle Receiver Idle Bit Or Receiver Overrun BitNF Receiver Noise Flag Bit FE Receiver Framing Error BitPE Receiver Parity Error Bit RPF -Reception-in-Progress Flag SCI Data RegisterSCI Baud Rate Register SCI Baud Rate PrescalingSCI Baud Rate Selection Baud Rate Divisor BDSCI Baud Rate Selection Examples Baud Rate Divisor PD Divisor BD180 Freescale Semiconductor Chapter System Integration Module SIM Signal Name ConventionsSignal Name Description Bus Timing Clock Startup from POR or LVI ResetSIM Bus Clock Control and Generation System Integration Module SIMExternal Pin Reset Reset and System InitializationClocks in Wait Mode Reset and System InitializationPIN Bit Set Timing Active Resets from Internal SourcesReset Type Number of Cycles Required to Set PIN Power-On Reset POR Computer Operating Properly COP ResetSIM Counter SIM Counter During Power-On ResetSIM Counter and Reset States Exception Control Exception ControlInterrupts Interrupt Processing Interrupt Recovery Hardware InterruptsSoftware Interrupt SWI Instruction Low-Power ModeReset SIM Registers SIM RegistersSIM Break Status Register Ilop Illegal Opcode Reset Bit SIM Reset Status RegisterPIN External Reset Bit Ilad Illegal Address Reset Bit opcode fetches onlySIM Break Flag Control Register 194 Freescale Semiconductor Pin Name Conventions Chapter Serial Peripheral Interface Module SPIPin Name Conventions Block Diagram Highlighting SPI Block and Pins Serial Peripheral Interface Module SPISPI Module Block Diagram Master Mode Serial Peripheral Interface Module SPI AddrTransmission Formats Slave ModeClock Phase and Polarity Controls Transmission FormatsTransmission Format When Cpha = Transmission Format Cpha =Transmission Initiation Latency Transmission Start Delay Master Error Conditions Error ConditionsOverflow Error Mode Fault Error 10. Clearing Sprf When Ovrf Interrupt Is Not EnabledFreescale Semiconductor 205 SPI Interrupts Flag RequestQueuing Transmission Data Resetting the SPIResetting the SPI 15.11 I/O Signals 12. SPRF/SPTE CPU Interrupt TimingMosi Master Out/Slave SignalsMiso Master In/Slave Out Spsck Serial Clock15.12 I/O Registers SPI ConfigurationSPI Configuration State of SS Logic VSS Clock GroundSpmstr SPI Master Bit Cpha Clock Phase BitSpwom SPI Wired-OR Mode Bit Cpol Clock Polarity BitErrie Error Interrupt Enable Bit SPE SPI Enable BitSPTIE- SPI Transmit Interrupt Enable Bit SPI Status and Control RegisterOvrf Overflow Bit Modf Mode Fault BitModfen Mode Fault Enable Bit Spte SPI Transmitter Empty BitSPI Data Register SPI Master Baud Rate SelectionChapter Timer Interface a Tima 2is a block diagram of the TimaBlock Diagram Highlighting Tima Block and Pins Timer Interface a TimaTima Block Diagram Timer Interface a Tima Addr Register Name Bit TIM I/O Register SummaryTima Counter Prescaler Input CaptureOutput Compare Unbuffered Output ComparePulse-Width Modulation PWM Buffered Output CompareUnbuffered PWM Signal Generation PWM Period and Pulse WidthBuffered PWM Signal Generation PWM Initialization224 Freescale Semiconductor 16.7 I/O Registers 16.6 I/O SignalsTima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A Tima Clock Pin PTE3/TCLKATstop Tima Stop Bit Toie Tima Overflow Interrupt Enable BitTrst Tima Reset Bit Prescaler Selection Tima Counter RegistersPS20 Prescaler Select Bits PS20 Tima Clock SourceTima Counter Modulo Registers Tima Channel Status and Control RegistersCHxIE Channel x Interrupt Enable Bit ELSxB and ELSxA Edge/Level Select Bits MSxB Mode Select Bit BMSxA Mode Select Bit a TOVx Toggle-On-Overflow Bit MSxBMSxA ELSxBELSxA Mode ConfigurationMode, Edge, and Level Selection CHxMAX Channel x Maximum Duty Cycle BitTima Channel Registers 10. Tima Channel Registers10. Tima Channel Registers TACH0H/L-TACH3H/L 234 Freescale Semiconductor Chapter Timer Interface B Timb Timb module is not available in the 56-pin SdipBlock Diagram Highlighting Timb Block and Pins Timer Interface B TimbTimb Block Diagram Timer Interface B Timb Addr Register Name Bit Timb Counter PrescalerFreescale Semiconductor 239 240 Freescale Semiconductor Freescale Semiconductor 241 242 Freescale Semiconductor Timb Clock Pin PTE0/TCLKB 17.6 I/O SignalsTimb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1B Timb Status and Control Register Toie Timb Overflow Interrupt Enable Bit17.7 I/O Registers PS20 Timb Clock Source Trst Timb Reset BitTstop Timb Stop Bit Timb Counter Registers Timb Counter Modulo RegistersTimb Channel Status and Control Registers 248 Freescale Semiconductor PWM Timb Channel Registers 10. Timb Channel Registers TBCH0H/L-TBCH1H/LFunctional Description Chapter Development SupportBreak Module BRK Flag Protection During Break InterruptsBreak Module Block Diagram Development SupportLow-Power Modes Break Module RegistersBreak Address Registers Break Status and Control RegisterBrka Break Active Bit Break Flag Control Register Monitor ROM MONBreak Status Register Monitor ROM MONNormal Monitor Mode Entering Monitor ModeMode Differences Monitor Mode Circuit Monitor Mode Signal Requirements and Options $FFFFForced Monitor Mode Data FormatEchoing Break SignalCommands Iread Indexed Read Command Read Read Memory CommandWrite Write Memory Command Command SequenceRUN Run User Program Command Iwrite Indexed Write CommandReadsp Read Stack Pointer Command Monitor Baud Rate Selection SecurityBaud Rate 13. Monitor Mode Entry Timing Absolute Maximum Ratings Chapter Electrical SpecificationsCharacteristic1 Symbol Value Unit Characteristic Symbol Value Unit Thermal CharacteristicsElectrical Specifications Functional Operating RangeCharacteristic1 Symbol Min Typ2 Max Unit DC Electrical CharacteristicsDC Electrical Characteristics Characteristic Symbol Min Max Unit Flash Memory CharacteristicsCharacteristic Symbol Min Typ Max Unit Control TimingDiagram Characteristic2 Symbol Min Max Unit Number1 Serial Peripheral Interface CharacteristicsSerial Peripheral Interface Characteristics SPI Master Timing SPI Slave Timing Characteristic Symbol Min Typ Max TImer Interface Module CharacteristicsClock Generation Module Component Specifications CGM Operating ConditionsDescription Symbol Min Typ Max CGM Acquisition/Lock Time SpecificationsCGM Acquisition/Lock Time Specifications Analog-to-Digital Converter ADC Characteristics 3FFOrder Numbers Chapter Ordering Information and Mechanical SpecificationsOrder Numbers MC Order Number OperatingOrdering Information and Mechanical Specifications 20.3 64-Pin Plastic Quad Flat Pack QFP20.4 56-Pin Shrink Dual In-Line Package Sdip Pin Shrink Dual In-Line Package Sdip278 Freescale Semiconductor Appendix a MC68HC908MR16 Figure A-1. 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