Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual Character Reception, Data Sampling

Functional Description

13.3.3.2 Character Reception

During an SCI reception, the receive shift register shifts characters in from the PTF4/RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.

After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request.

13.3.3.3 Data Sampling

The receiver samples the PTF4/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times (see Figure 13-7):

•After every start bit

•After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at RT8, RT9, and RT10 return a valid 1 and the majority of the next RT8, RT9, and RT10 samples return a valid 0)

PTF4/RxD

SAMPLES

RT

CLOCK

RT CLOCK STATE

RT CLOCK RESET

START BIT

START BIT	START BIT	DATA
QUALIFICATION	VERIFICATION	SAMPLING

RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16

LSB

RT1 RT2 RT3 RT4

Figure 13-7. Receiver Data Sampling

To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-1summarizes the results of the start bit verification samples.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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