Freescale Semiconductor MC68HC908MR16 manual Data Direction Register B, Port B Pin Functions

Port B

10.3.2 Data Direction Register B

Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.

Address:

Read:

Write:

Reset:

$0005
Bit 7	6	5	4	3	2	1	Bit 0
DDRB7	DDRB6	DDRB5	DDRB4	DDRB3	DDRB2	DDRB1	DDRB0
0	0	0	0	0	0	0	0

Figure 10-6. Data Direction Register B (DDRB)

DDRB[7:0] — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs.

1 = Corresponding port B pin configured as output

0 = Corresponding port B pin configured as input

NOTE

Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1.

Figure 10-7shows the port B I/O logic.

INTERNAL DATA BUS

READ DDRB ($0005)

WRITE DDRB ($0005)

DDRBx

RESET

WRITE PTB ($0001)

PTBx

READ PTB ($0001)

PTBx

Figure 10-7. Port B I/O Circuit

When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-2summarizes the operation of the port B pins.

Table 10-2. Port B Pin Functions

DDRB Bit	PTB Bit	I/O Pin Mode	Accesses to DDRB	Accesses to PTB
			Read/Write	Read	Write
0	X(1)	Input, Hi-Z(2)	DDRB[7:0]	Pin	PTB[7:0](3)
1	X	Output	DDRB[7:0]	PTB[7:0]	PTB[7:0]

1.X = don’t care

2.Hi-Z = high impedance

3.Writing affects data register, but does not affect input.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor 105