Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Transmission Start Delay Master

Serial Peripheral Interface Module (SPI)

When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. See Figure 15-8The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 15-8. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.

WRITE	INITIATION DELAY
TO SPDR
BUS
CLOCK
MOSI	MSB	BIT 6	BIT 5
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE	1	2	3
NUMBER
	INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN

WRITE

TO SPDR

BUS
CLOCK
						SPSCK = INTERNAL CLOCK ⎟ 2;
			EARLIEST	LATEST
							2 POSSIBLE START POINTS
		WRITE
BUS	TO SPDR
CLOCK
							SPSCK =	INTERNAL	CLOCK ⎟
			EARLIEST							8;	LATEST
		WRITE					8 POSSIBLE START POINTS
BUS	TO SPDR
CLOCK
			EARLIEST			SPSCK = INTERNAL CLOCK ⎟ 32;					LATEST
		WRITE					32 POSSIBLE START POINTS
BUS	TO SPDR
CLOCK
			EARLIEST		SPSCK = INTERNAL CLOCK ⎟ 128;						LATEST
						128 POSSIBLE START POINTS

Figure 15-8. Transmission Start Delay (Master)

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

202 Freescale Semiconductor