Serial Communications Interface Module (SCI)

13.7.4 SCI Status Register 1

SCI status register 1 (SCS1) contains flags to signal these conditions:

Transfer of SCDR data to transmit shift register complete

Transmission complete

Transfer of receive shift register data to SCDR complete

Receiver input idle

Receiver overrun

Noisy data

Framing error

Parity error

Address:

$003B

 

 

 

 

 

 

 

 

Bit 7

6

5

4

3

2

1

Bit 0

 

 

 

 

 

 

 

 

 

Read:

SCTE

TC

SCRF

IDLE

OR

NF

FE

PE

 

 

 

 

 

 

 

 

 

Write:

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

Reset:

1

1

0

0

0

0

0

0

R

= Reserved

Figure 13-11. SCI Status Register 1 (SCS1)

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.

1 = SCDR data transferred to transmit shift register

0 = SCDR data not transferred to transmit shift register

TC — Transmission Complete Bit

This read-only bit is set when the SCTE bit is set and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit.

1 = No transmission in progress

0 = Transmission in progress

SCRF — SCI Receiver Full Bit

This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.

1 = Received data available in SCDR

0 = Data not available in SCDR

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

174

Freescale Semiconductor

Page 174
Image 174
Freescale Semiconductor MC68HC908MR32 manual SCI Status Register, TC Transmission Complete Bit, Scrf SCI Receiver Full Bit

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

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