Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Mode Fault Error

Serial Peripheral Interface Module (SPI)

In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 15-10illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF interrupt to the CPU by setting the ERRIE bit.

	BYTE 1					BYTE 2		BYTE 3					BYTE 4
SPI RECEIVE							5			7					11
		1
COMPLETE
SPRF
OVRF
READ
			2		4				6			9				12		14
SPSCR
READ				3							8			10			13
SPDR

1BYTE 1 SETS SPRF BIT.

2CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.

3CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT.

4CPU READS SPSCR AGAIN TO CHECK OVRF BIT.

5BYTE 2 SETS SPRF BIT.

6CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.

7BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.

8CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT.

9CPU READS SPSCR AGAIN TO CHECK OVRF BIT.

10CPU READS BYTE 2 SPDR, CLEARING OVRF BIT.

11BYTE 4 SETS SPRF BIT.

12CPU READS SPSCR.

13CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT.

14CPU READS SPSCR AGAIN TO CHECK OVRF BIT.

Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled

15.6.2 Mode Fault Error

Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.

To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:

•The SS pin of a slave SPI goes high during a transmission.

•The SS pin of a master SPI goes low at any time.

For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared.

MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 15-11.It is not possible to enable MODF or

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

204 Freescale Semiconductor