Opcode Map, 9ED 9EE | Freescale Semiconductor MC68HC908MR32 manual

90

Freescale Semiconductor

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Table 7-2. Opcode Map

		Bit Manipulation					Branch							Read-Modify-Write									Control									Register/Memory
			DIR	DIR				REL		DIR		INH			INH		IX1		SP1		IX		INH		INH		IMM		DIR		EXT		IX2		SP2		IX1		SP1		IX
MSB			0	1				2		3		4			5		6		9E6		7		8		9		A		B		C		D		9ED		E		9EE		F
LSB			0	1				2		3		4			5		6		9E6		7		8		9		A		B		C		D		9ED		E		9EE		F
LSB

0			5		4			3		4		1			1		4		5		3		7		3		2		3		4		4		5		3		4		2
0		BRSET0		BSET0				BRA		NEG		NEGA			NEGX		NEG		NEG		NEG		RTI		BGE		SUB		SUB		SUB		SUB		SUB		SUB		SUB		SUB
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	2	REL	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
1			5		4			3		5		4			4		5		6		4		4		3		2		3		4		4		5		3		4		2
1		BRCLR0		BCLR0				BRN		CBEQ	CBEQA			CBEQX			CBEQ		CBEQ		CBEQ		RTS		BLT		CMP		CMP		CMP		CMP		CMP		CMP		CMP		CMP
		3	DIR	2	DIR		2	REL	3	DIR	3	IMM		3	IMM	3	IX1+	4	SP1	2	IX+	1	INH	2	REL	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
2			5		4			3				5			7		3				2				3		2		3		4		4		5		3		4		2
2		BRSET1		BSET1				BHI				MUL			DIV		NSA				DAA				BGT		SBC		SBC		SBC		SBC		SBC		SBC		SBC		SBC
		3	DIR	2	DIR		2	REL			1	INH		1	INH	1	INH			1	INH			2	REL	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
3			5		4			3		4		1			1		4		5		3		9		3		2		3		4		4		5		3		4		2
3		BRCLR1		BCLR1				BLS		COM	COMA			COMX			COM		COM		COM		SWI		BLE		CPX		CPX		CPX		CPX		CPX		CPX		CPX		CPX
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	2	REL	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
4			5		4			3		4		1			1		4		5		3		2		2		2		3		4		4		5		3		4		2
4		BRSET2		BSET2				BCC		LSR		LSRA			LSRX		LSR		LSR		LSR		TAP		TXS		AND		AND		AND		AND		AND		AND		AND		AND
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
5			5		4			3		4		3			4		3				4		1		2		2		3		4		4		5		3		4		2
5		BRCLR2		BCLR2				BCS		STHX		LDHX			LDHX		CPHX				CPHX		TPA		TSX		BIT		BIT		BIT		BIT		BIT		BIT		BIT		BIT
		3	DIR	2	DIR		2	REL	2	DIR	3	IMM		2	DIR	3	IMM			2	DIR	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
6			5		4			3		4		1			1		4		5		3		2				2		3		4		4		5		3		4		2
6		BRSET3		BSET3				BNE		ROR	RORA			RORX			ROR		ROR		ROR		PULA				LDA		LDA		LDA		LDA		LDA		LDA		LDA		LDA
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH			2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
7			5		4			3		4		1			1		4		5		3		2		1		2		3		4		4		5		3		4		2
7		BRCLR3		BCLR3				BEQ		ASR		ASRA			ASRX		ASR		ASR		ASR		PSHA		TAX		AIS		STA		STA		STA		STA		STA		STA		STA
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
8			5		4			3		4		1			1		4		5		3		2		1		2		3		4		4		5		3		4		2
8		BRSET4		BSET4				BHCC		LSL		LSLA			LSLX		LSL		LSL		LSL		PULX		CLC		EOR		EOR		EOR		EOR		EOR		EOR		EOR		EOR
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
9			5		4			3		4		1			1		4		5		3		2		1		2		3		4		4		5		3		4		2
9		BRCLR4		BCLR4				BHCS		ROL		ROLA			ROLX		ROL		ROL		ROL		PSHX		SEC		ADC		ADC		ADC		ADC		ADC		ADC		ADC		ADC
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
A			5		4			3		4		1			1		4		5		3		2		2		2		3		4		4		5		3		4		2
A		BRSET5		BSET5				BPL		DEC		DECA			DECX		DEC		DEC		DEC		PULH		CLI		ORA		ORA		ORA		ORA		ORA		ORA		ORA		ORA
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
B			5		4			3		5		3			3		5		6		4		2		2		2		3		4		4		5		3		4		2
B		BRCLR5		BCLR5				BMI		DBNZ	DBNZA			DBNZX			DBNZ		DBNZ		DBNZ		PSHH		SEI		ADD		ADD		ADD		ADD		ADD		ADD		ADD		ADD
		3	DIR	2	DIR		2	REL	3	DIR	2	INH		2	INH	3	IX1	4	SP1	2	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
C			5		4			3		4		1			1		4		5		3		1		1				2		3		4				3				2
C		BRSET6		BSET6				BMC		INC		INCA			INCX		INC		INC		INC		CLRH		RSP				JMP		JMP		JMP				JMP				JMP
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH			2	DIR	3	EXT	3	IX2			2	IX1			1	IX
D			5		4			3		3		1			1		3		4		2				1		4		4		5		6				5				4
D		BRCLR6		BCLR6				BMS		TST		TSTA			TSTX		TST		TST		TST				NOP		BSR		JSR		JSR		JSR				JSR				JSR
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX			1	INH	2	REL	2	DIR	3	EXT	3	IX2			2	IX1			1	IX
E			5		4			3				5			4		4				4		1				2		3		4		4		5		3		4		2
E		BRSET7		BSET7				BIL				MOV			MOV		MOV				MOV		STOP		*		LDX		LDX		LDX		LDX		LDX		LDX		LDX		LDX
		3	DIR	2	DIR		2	REL			3	DD		2	DIX+	3	IMD			2	IX+D	1	INH		*	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
F			5		4			3		3		1			1		3		4		2		1		1		2		3		4		4		5		3		4		2
F		BRCLR7		BCLR7				BIH		CLR		CLRA			CLRX		CLR		CLR		CLR		WAIT		TXA		AIX		STX		STX		STX		STX		STX		STX		STX
		3	DIR	2	DIR		2	REL	2	DIR	1	INH		1	INH	2	IX1	3	SP1	1	IX	1	INH	1	INH	2	IMM	2	DIR	3	EXT	3	IX2	4	SP2	2	IX1	3	SP1	1	IX
INH	Inherent			REL		Relative						SP1	Stack Pointer, 8-Bit Offset
INH	Inherent			REL		Relative						SP1	Stack Pointer, 8-Bit Offset																MSB		0	High Byte of Opcode in Hexadecimal
IMM	Immediate			IX		Indexed, No Offset						SP2	Stack Pointer, 16-Bit Offset															LSB			0	High Byte of Opcode in Hexadecimal
DIR	Direct			IX1		Indexed, 8-Bit Offset						IX+	Indexed, No Offset with															LSB
EXT	Extended			IX2		Indexed, 16-Bit Offset							Post Increment																		5	Cycles
DD	Direct-Direct			IMD		Immediate-Direct						IX1+ Indexed, 1-Byte Offset with									Low Byte of Opcode in Hexadecimal								0	BRSET0		Opcode Mnemonic
IX+D Indexed-Direct				DIX+ Direct-Indexed									Post Increment																	3	DIR	Number of Bytes / Addressing Mode
*Pre-byte for stack pointer indexed instructions
*Pre-byte for stack pointer indexed instructions

Central Processor Unit (CPU)

Image 90

Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Opcode Map, 9ED 9EE

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.

Contents

MC68HC908MR32 MC68HC908MR16 Page Data Sheet MC68HC908MR32 MC68HC908MR16 Data Sheet, RevMC68HC908MR32 MC68HC908MR16 Revision History Revision HistoryDate Revision Description Level Numbers List of Chapters List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Table of Contents Table of Contents Chapter Analog-to-Digital Converter ADCChapter Clock Generator Module CGM Chapter Configuration Register Config Chapter Computer Operating Properly COP Chapter Central Processor Unit CPU Chapter External Interrupt IRQChapter Low-Voltage Inhibit LVI Chapter Power-On Reset POR Chapter Input/Output I/O Ports PortsChapter Pulse-Width Modulator for Motor Control Pwmmc Chapter Serial Communications Interface Module SCI Chapter System Integration Module SIM Chapter Serial Peripheral Interface Module SPI Chapter Timer Interface a Tima Chapter Timer Interface B Timb Chapter Development Support Chapter Electrical Specifications Chapter Ordering Information and Mechanical Specifications Features Chapter General DescriptionIntroduction MCU Block Diagram General Description Diagram MCU Block Pin Assignments Pin QFP Pin Assignments Pin Sdip Pin Assignments Pin Assignments External Reset Pin RST Power Supply Pins VDD and VSSOscillator Pins OSC1 and OSC2 CGM Power Supply Pins Vdda and Vssad Port B I/O Pins PTB7/ATD7-PTB0/ATD0 Analog Power Supply Pins Vddad and VssadPort a Input/Output I/O Pins PTA7-PTA0 Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8 Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK PWM Ground Pin Pwmgnd Chapter Memory Unimplemented Memory LocationsReserved Memory Locations I/O Section Memory MapMemory MC68HC908MR32 Memory Map Memory Map Control, Status, and Data Registers Summary Sheet 1 Memory Addr Control, Status, and Data Registers Summary Sheet 2 Memory Map Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 3 Memory Addr Register Name Control, Status, and Data Registers Summary Sheet 4 Control, Status, and Data Registers Summary Sheet 5 Memory Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 6 Addr Register Name Control, Status, and Data Registers Summary Sheet 7 Control, Status, and Data Registers Summary Sheet 8 Vector Addresses Address Vector Low Monitor ROM Random-Access Memory RAMMonitor ROM Address Vector Flash Memory Flash Flash Control Register Mass Mass Erase Control Bit Hven High-Voltage Enable BitFlash Page Erase Operation Erase Erase Control Bit Flash Mass Erase Operation Flash Program Operation Only bytes which are currently $FF may be programmed Flash Programming Flowchart Flash Block Protection Flash Block Protect Register Wait Mode Stop ModeExamples of Protect Start Address Chapter Analog-to-Digital Converter ADC Functional Description Block Diagram Highlighting ADC Block and Pins Analog-to-Digital Converter ADC ADC Port I/O Pins Voltage ConversionFunctional Description Conversion Time Continuous ConversionResult Justification Bit Truncation Mode Error Monotonicity Wait Mode I/O SignalsInterrupts ADC External Connections I/O RegistersADC Voltage In Advin 6.2 ANx Aien ADC Interrupt Enable Bit ADC Status and Control Register Mux Channel Select Input Select ADC Data Register High ADC Data Register Low ADC Clock Register ADC Clock Divide RatioADC Clock Rate Analog-to-Digital Converter ADC Chapter Clock Generator Module CGM Cgmvclk CGM Block Diagram Clock Generator Module CGM Phase-Locked Loop Circuit PLL Crystal Oscillator CircuitPLL Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Variable DefinitionsVariable Definition Base Clock Selector Circuit Special Programming Exceptions CGM External Connections CGM External Connections Crystal Amplifier Input Pin OSC1 PLL Analog Power Pin VddaOscillator Enable Signal Simoscen Crystal Amplifier Output Pin OSC2 CGM Base Clock Output Cgmout Crystal Output Frequency Signal CgmxclkCGM Registers CGM CPU Interrupt Cgmint Pllon PLL On Bit PLL Control RegisterPllf PLL Interrupt Flag BCS Base Clock Select Bit PLL Bandwidth Control Register Lock Lock Indicator BitACQ Acquisition Mode Bit PCTL30 Unimplemented Bits PBWC30 Reserved for Test PLL Programming RegisterXLD Crystal Loss Detect Bit VCO Frequency Multiplier N Selection VRS74 VCO Range Select Bits Interrupts Acquisition/Lock Time Specifications Acquisition/Lock Time DefinitionsParametric Influences on Reaction Time Acquisition/Lock Time Specifications Choosing a Filter CapacitorReaction Time Calculation Frequency Chapter Configuration Register Config Configuration Register COP Block Diagram Chapter Computer Operating Properly COP Reset Vector Fetch Power-On ResetInternal Reset Copctl Write Copd COP Disable Monitor ModeStop Mode COP Control Register Freescale Semiconductor Chapter Central Processor Unit CPU CPU Registers Accumulator Index RegisterCentral Processor Unit CPU Stack Pointer Program CounterCPU Registers Interrupt Mask Condition Code RegisterHalf-Carry Flag Negative Flag CPU During Break Interrupts Low-Power ModesArithmetic/Logic Unit ALU Zero Flag Instruction Set Summary Instruction Set Summary Sheet 1 Instruction Set Summary Sheet 2 Instruction Set SummarySource Operation Description On CCR Form Instruction Set Summary Sheet 3 Dbnz opr,rel Instruction Set Summary Sheet 4 JMP ,X Instruction Set Summary Sheet 5 Operation Description On CCR Form Opcode Map Instruction Set Summary Sheet 6Opcode Map Opcode Map 9ED 9EE IRQ Module Block Diagram Chapter External Interrupt IRQ IRQ Pin External Interrupt IRQ IRQ Interrupt Flowchart IRQ Pin IRQ Status and Control Register IRQ Status and Control Register Iscr Irqf IRQ Flag IRQ Status and Control Register Freescale Semiconductor LVI Module Block Diagram Chapter Low-Voltage Inhibit LVI Polled LVI Operation Forced Reset OperationFalse Reset Protection LVI Trip Selection Lviout Bit Indication LVI Status and Control RegisterLVI Interrupts LVI Status and Control Register 100 Freescale Semiconductor Chapter Input/Output I/O Ports Ports I/O Port Register Summary Input/Output I/O Ports Ports Addr Register Name Data Direction Register a Port aPort a Data Register Port a Port a Pin Functions Port BPort B Data Register Input/Output I/O Ports Ports Data Direction Register B Port B Pin FunctionsPort B Port C Port C Data RegisterData Direction Register C Port D Port DPort C Pin Functions PTC60 Port E Data Register PTD Bit Pin Mode Accesses to PTD ReadPort E Port D Pin Functions Port E Pin Functions Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTEData Direction Register E Port E Port F Port F Data RegisterData Direction Register F Port F Pin Functions Port F 112 Freescale Semiconductor Chapter Power-On Reset POR 114 Freescale Semiconductor Chapter Pulse-Width Modulator for Motor Control Pwmmc Block Diagram Highlighting Pwmmc Block and Pins Pulse-Width Modulator for Motor Control Pwmmc PWM Module Block Diagram Features Register Summary Sheet 2 Features Addr Register Name Bit Register Summary Sheet 3 Resolution Timebase Edge-Aligned PWM Positive Polarity Timebase Load Operation PWM GeneratorsPrescaler PWM Prescaler Reload Frequency Change PWM Interrupt Requests Center-Aligned PWM Value Loading PWM Data Overflow and Underflow Conditions PWM Data Overflow and Underflow ConditionsPWMVALxHPWMVALxL Condition PWM Value Used 12. Complementary Pairing Output Control Dead-Time Insertion Output Control 14. Dead-Time Generators 15. Effects of Dead-Time Insertion 17. Dead-Time and Small Pulse Widths Current Sense Pins Current Voltage On Current Correction Methods Current Correction Bits Correction Method ISENS1 and ISENS0 Output Polarity 20. Top/Bottom Correction for PWMs 1 21. PWM Polarity OUTx Bit Complementary Mode Independent Mode PWM Output Port ControlOUTx Bits 23. Dead-Time Insertion During Outctl = Fault Protection Fault Condition Input PinsFault Protection 26. PWM Disabling Scheme Fault Pin Filter Automatic Mode 28. PWM Disabling in Automatic Mode Manual Mode Software Output Disable Output Port Control 32. Pwmen and PWM Pins Initialization and the Pwmen Bit Control Logic Block PWM Operation in Wait ModePWM Operation in Wait Mode PWM Counter Registers PWM Counter Modulo Registers 35. PWM Counter Modulo Register High Pmodh PWMx Value Registers Control Logic Block PWM Control Register Disy Software Disable Bit for Bank Y BitPwmint PWM Interrupt Enable Bit Pwmf PWM Reload Flag Pwmen PWM Module Enable Bit LDOK- Load OK Bit IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1 IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3 IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5PRSC1 and PRSC0 PWM Prescaler Bits PWM Disable Mapping Write-Once Register Fault Control RegisterDead-Time Write-Once Register FINT3 Fault 3 Interrupt Enable Bit FINT2 Fault 2 Interrupt Enable BitFINT1 Fault 1 Interrupt Enable Bit Fault Status Register Fault Acknowledge Register DT1 Dead-Time 1 Bit PWM Output Control RegisterDT2 Dead-Time 2 Bit 10. OUTx Bits PWM Glossary PWM Glossary 48. PWM Load Cycle/Frequency Definition Chapter Serial Communications Interface Module SCI Block Diagram Highlighting SCI Block and Pins Serial Communications Interface Module SCI SCI Module Block Diagram Data Format Serial Communications Interface Module SCI Addr Transmitter SCI Transmitter Character Length Character TransmissionBreak Characters Inversion of Transmitted Output ReceiverIdle Characters Transmitter Interrupts SCI Receiver Block Diagram Character Reception Data Sampling Data Bit Recovery Stop Bit RecoveryStart Bit Verification Receiver Wakeup Framing ErrorsError Interrupts Receiver Interrupts 13.6 I/O Signals SCI During Break Module Interrupts13.6.1 PTF5/TxD Transmit Data 13.7 I/O Registers 13.6.2 PTF4/RxD Receive DataSCI Control Register PEN Parity Enable Bit Ensci Enable SCI BitMode Character Length Bit Txinv Transmit Inversion Bit Control Bits Character Format Tcie Transmission Complete Interrupt Enable BitCharacter Format Selection Start Data Parity Stop TE Transmitter Enable Bit Scrie SCI Receive Interrupt Enable BitIlie Idle Line Interrupt Enable Bit RE Receiver Enable Bit Feie Receiver Framing Error Interrupt Enable Bit Orie Receiver Overrun Interrupt Enable BitNeie Receiver Noise Error Interrupt Enable Bit Peie Receiver Parity Error Interrupt Enable Bit SCI Status Register TC Transmission Complete BitScrf SCI Receiver Full Bit Idle Receiver Idle Bit Or Receiver Overrun Bit FE Receiver Framing Error Bit PE Receiver Parity Error BitNF Receiver Noise Flag Bit RPF -Reception-in-Progress Flag SCI Data RegisterSCI Baud Rate Register SCI Baud Rate Prescaling SCI Baud Rate Selection Baud Rate Divisor BD SCI Baud Rate Selection Examples Baud Rate Divisor PD Divisor BD 180 Freescale Semiconductor Signal Name Conventions Signal Name DescriptionChapter System Integration Module SIM Bus Timing Clock Startup from POR or LVI ResetSIM Bus Clock Control and Generation System Integration Module SIM External Pin Reset Reset and System InitializationClocks in Wait Mode Reset and System Initialization Active Resets from Internal Sources Reset Type Number of Cycles Required to Set PINPIN Bit Set Timing Power-On Reset POR Computer Operating Properly COP Reset SIM Counter During Power-On Reset SIM Counter and Reset StatesSIM Counter Exception Control InterruptsException Control Interrupt Processing Interrupt Recovery Hardware Interrupts Low-Power Mode ResetSoftware Interrupt SWI Instruction SIM Registers SIM Break Status RegisterSIM Registers Ilop Illegal Opcode Reset Bit SIM Reset Status RegisterPIN External Reset Bit Ilad Illegal Address Reset Bit opcode fetches only SIM Break Flag Control Register 194 Freescale Semiconductor Chapter Serial Peripheral Interface Module SPI Pin Name ConventionsPin Name Conventions Block Diagram Highlighting SPI Block and Pins Serial Peripheral Interface Module SPI SPI Module Block Diagram Master Mode Serial Peripheral Interface Module SPI Addr Transmission Formats Slave ModeClock Phase and Polarity Controls Transmission Formats Transmission Format When Cpha = Transmission Format Cpha = Transmission Initiation Latency Transmission Start Delay Master Error Conditions Overflow ErrorError Conditions Mode Fault Error 10. Clearing Sprf When Ovrf Interrupt Is Not Enabled Freescale Semiconductor 205 SPI Interrupts Flag Request Resetting the SPI Resetting the SPIQueuing Transmission Data 15.11 I/O Signals 12. SPRF/SPTE CPU Interrupt Timing Mosi Master Out/Slave SignalsMiso Master In/Slave Out Spsck Serial Clock 15.12 I/O Registers SPI ConfigurationSPI Configuration State of SS Logic VSS Clock Ground Spmstr SPI Master Bit Cpha Clock Phase BitSpwom SPI Wired-OR Mode Bit Cpol Clock Polarity Bit Errie Error Interrupt Enable Bit SPE SPI Enable BitSPTIE- SPI Transmit Interrupt Enable Bit SPI Status and Control Register Ovrf Overflow Bit Modf Mode Fault BitModfen Mode Fault Enable Bit Spte SPI Transmitter Empty Bit SPI Data Register SPI Master Baud Rate Selection Chapter Timer Interface a Tima 2is a block diagram of the Tima Block Diagram Highlighting Tima Block and Pins Timer Interface a Tima Tima Block Diagram Timer Interface a Tima Addr Register Name Bit TIM I/O Register Summary Tima Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Pulse-Width Modulation PWM Buffered Output Compare Unbuffered PWM Signal Generation PWM Period and Pulse Width Buffered PWM Signal Generation PWM Initialization 224 Freescale Semiconductor 16.7 I/O Registers 16.6 I/O SignalsTima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A Tima Clock Pin PTE3/TCLKA Toie Tima Overflow Interrupt Enable Bit Trst Tima Reset BitTstop Tima Stop Bit Prescaler Selection Tima Counter RegistersPS20 Prescaler Select Bits PS20 Tima Clock Source Tima Counter Modulo Registers Tima Channel Status and Control Registers CHxIE Channel x Interrupt Enable Bit MSxB Mode Select Bit B MSxA Mode Select Bit aELSxB and ELSxA Edge/Level Select Bits TOVx Toggle-On-Overflow Bit MSxBMSxA ELSxBELSxA Mode ConfigurationMode, Edge, and Level Selection CHxMAX Channel x Maximum Duty Cycle Bit Tima Channel Registers 10. Tima Channel Registers 10. Tima Channel Registers TACH0H/L-TACH3H/L 234 Freescale Semiconductor Chapter Timer Interface B Timb Timb module is not available in the 56-pin Sdip Block Diagram Highlighting Timb Block and Pins Timer Interface B Timb Timb Block Diagram Timer Interface B Timb Addr Register Name Bit Timb Counter Prescaler Freescale Semiconductor 239 240 Freescale Semiconductor Freescale Semiconductor 241 242 Freescale Semiconductor 17.6 I/O Signals Timb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1BTimb Clock Pin PTE0/TCLKB Toie Timb Overflow Interrupt Enable Bit 17.7 I/O RegistersTimb Status and Control Register Trst Timb Reset Bit Tstop Timb Stop BitPS20 Timb Clock Source Timb Counter Registers Timb Counter Modulo Registers Timb Channel Status and Control Registers 248 Freescale Semiconductor PWM Timb Channel Registers 10. Timb Channel Registers TBCH0H/L-TBCH1H/L Functional Description Chapter Development SupportBreak Module BRK Flag Protection During Break Interrupts Break Module Block Diagram Development Support Low-Power Modes Break Module Registers Break Status and Control Register Brka Break Active BitBreak Address Registers Break Flag Control Register Monitor ROM MONBreak Status Register Monitor ROM MON Entering Monitor Mode Mode DifferencesNormal Monitor Mode Monitor Mode Circuit Monitor Mode Signal Requirements and Options $FFFF Forced Monitor Mode Data Format Break Signal CommandsEchoing Iread Indexed Read Command Read Read Memory CommandWrite Write Memory Command Command Sequence Iwrite Indexed Write Command Readsp Read Stack Pointer CommandRUN Run User Program Command Security Baud RateMonitor Baud Rate Selection 13. Monitor Mode Entry Timing Chapter Electrical Specifications Characteristic1 Symbol Value UnitAbsolute Maximum Ratings Characteristic Symbol Value Unit Thermal CharacteristicsElectrical Specifications Functional Operating Range DC Electrical Characteristics DC Electrical CharacteristicsCharacteristic1 Symbol Min Typ2 Max Unit Characteristic Symbol Min Max Unit Flash Memory CharacteristicsCharacteristic Symbol Min Typ Max Unit Control Timing Serial Peripheral Interface Characteristics Serial Peripheral Interface CharacteristicsDiagram Characteristic2 Symbol Min Max Unit Number1 SPI Master Timing SPI Slave Timing Characteristic Symbol Min Typ Max TImer Interface Module CharacteristicsClock Generation Module Component Specifications CGM Operating Conditions CGM Acquisition/Lock Time Specifications CGM Acquisition/Lock Time SpecificationsDescription Symbol Min Typ Max Analog-to-Digital Converter ADC Characteristics 3FF Order Numbers Chapter Ordering Information and Mechanical SpecificationsOrder Numbers MC Order Number Operating Ordering Information and Mechanical Specifications 20.3 64-Pin Plastic Quad Flat Pack QFP 20.4 56-Pin Shrink Dual In-Line Package Sdip Pin Shrink Dual In-Line Package Sdip 278 Freescale Semiconductor Appendix a MC68HC908MR16 Figure A-1. MC68HC908MR16 Memory Map MC68HC908MR16Page How to Reach Us