Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 SIM Registers, SIM Break Status Register

SIM Registers

32

CYCLES

IAB		$6E0B
IDB
	$A6	$A6	$A6
RST

CGMXCLK

32

CYCLES

RST VCT H RST VCT L

Figure 14-13. Wait Recovery from Internal Reset

14.6.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is hard wired at the normal delay of 4096 CGMXCLK cycles.

It is important to note that when using the PWM generator, its outputs will stop toggling when stop mode is entered. The PWM module must be disabled before entering stop mode to prevent external inverter failure.

14.7 SIM Registers

This subsection describes the SIM registers.

14.7.1 SIM Break Status Register

The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode.

Address:

Read:

Write:

Reset:

$FE00
BIt 7	6	5	4	3		2	1	Bit 0
R	R	R	R		R	R	SBSW	R
							Note(1)
							0
R	= Reserved			Note 1. Writing a logic 0 clears SBSW.

Figure 14-14. SIM Break Status Register (SBSR)

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.

1 = Wait mode was exited by break interrupt.

0 = Wait mode was not exited by break interrupt.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor 191