Central Processor Unit (CPU)

Table 7-1. Instruction Set Summary (Sheet 3 of 6)

 

 

 

 

 

 

 

 

Effect

 

 

Address Mode

Opcode

Operand

Cycles

Source

Operation

 

Description

 

on CCR

 

 

 

 

 

Form

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

H

I

N

Z

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR opr

 

 

M ← $00

 

 

 

 

 

 

 

 

DIR

3F

dd

3

CLRA

 

 

 

A ← $00

 

 

 

 

 

 

 

 

INH

4F

 

1

CLRX

 

 

 

X ← $00

 

 

 

 

 

 

 

 

INH

5F

 

1

CLRH

Clear

 

 

H ← $00

0

–

 

–

0

 

1

–

INH

8C

 

1

CLR opr,X

 

 

M ← $00

 

 

 

 

 

 

 

 

IX1

6F

ff

3

CLR ,X

 

 

M ← $00

 

 

 

 

 

 

 

 

IX

7F

 

2

CLR opr,SP

 

 

M ← $00

 

 

 

 

 

 

 

 

SP1

9E6F

ff

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CMP #opr

 

 

 

 

 

 

 

 

 

 

 

 

 

IMM

A1

ii

2

CMP opr

 

 

 

 

 

 

 

 

 

 

 

 

 

DIR

B1

dd

3

CMP opr

 

 

 

 

 

 

 

 

 

 

 

 

 

EXT

C1

hh ll

4

CMP opr,X

Compare A with M

 

 

(A) – (M)



–

 

–



 





IX2

D1

ee ff

4

CMP opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

IX1

E1

ff

3

CMP ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

IX

F1

 

2

CMP opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1

9EE1

ff

4

CMP opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

SP2

9ED1

ee ff

5

COM opr

 

M ← (

 

) = $FF – (M)

 

 

 

 

 

 

 

 

DIR

33

dd

4

 

M

 

 

 

 

 

 

 

 

COMA

 

A

← (A) = $FF – (M)

 

 

 

 

 

 

 

 

INH

43

 

1

COMX

Complement (One’s Complement)

X

← (X) = $FF – (M)

0

–

 

–



 



1

INH

53

 

1

COM opr,X

M

← (M) = $FF – (M)

 

 

IX1

63

ff

4

COM ,X

 

M

← (M) = $FF – (M)

 

 

 

 

 

 

 

 

IX

73

 

3

COM opr,SP

 

M

← (M) = $FF – (M)

 

 

 

 

 

 

 

 

SP1

9E63

ff

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPHX #opr

Compare H:X with M

 

(H:X) – (M:M + 1)



–

 

–



 





IMM

65

ii ii+1

3

CPHX opr

 

 

 

 

 

 

 

 

 

 

 

 

 

DIR

75

dd

4

CPX #opr

 

 

 

 

 

 

 

 

 

 

 

 

 

IMM

A3

ii

2

CPX opr

 

 

 

 

 

 

 

 

 

 

 

 

 

DIR

B3

dd

3

CPX opr

 

 

 

 

 

 

 

 

 

 

 

 

 

EXT

C3

hh ll

4

CPX ,X

Compare X with M

 

 

(X) – (M)



–

 

–



 





IX2

D3

ee ff

4

CPX opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

IX1

E3

ff

3

CPX opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

IX

F3

 

2

CPX opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1

9EE3

ff

4

CPX opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

SP2

9ED3

ee ff

5

DAA

Decimal Adjust A

 

 

 

(A)10

U

–

 

–



 





INH

72

 

2

 

 

A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1

 

 

 

 

 

 

 

 

 

 

 

5

DBNZ opr,rel

 

PC ← (PC) + 3 + rel ? (result) ≠ 0

 

 

 

 

 

 

 

 

DIR

3B

dd rr

 

 

 

 

 

 

 

 

 

3

DBNZA rel

 

PC ← (PC) + 2 + rel ? (result) ≠ 0

 

 

 

 

 

 

 

 

INH

4B

rr

 

 

 

 

 

 

 

 

 

3

DBNZX rel

Decrement and Branch if Not Zero

PC ← (PC) + 2 + rel ? (result) ≠ 0

–

–

 

–

–

 

–

–

INH

5B

rr

 

 

5

DBNZ opr,X,rel

 

PC ← (PC) + 3 + rel ? (result) ≠ 0

 

 

 

 

 

 

 

 

IX1

6B

ff rr

 

 

 

 

 

 

 

 

 

4

DBNZ X,rel

 

PC ← (PC) + 2 + rel ? (result) ≠ 0

 

 

 

 

 

 

 

 

IX

7B

rr

 

 

 

 

 

 

 

 

 

6

DBNZ opr,SP,rel

 

PC ← (PC) + 4 + rel ? (result) ≠ 0

 

 

 

 

 

 

 

 

SP1

9E6B

ff rr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC opr

 

 

M ← (M) – 1

 

 

 

 

 

 

 

 

DIR

3A

dd

4

DECA

 

 

A ← (A) – 1

 

 

 

 

 

 

 

 

INH

4A

 

1

DECX

Decrement

 

X ← (X) – 1



–

 

–



 



–

INH

5A

 

1

DEC opr,X

 

M ← (M) – 1

 

 

IX1

6A

ff

4

DEC ,X

 

 

M ← (M) – 1

 

 

 

 

 

 

 

 

IX

7A

 

3

DEC opr,SP

 

 

M ← (M) – 1

 

 

 

 

 

 

 

 

SP1

9E6A

ff

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIV

Divide

 

A ← (H:A)/(X)

–

–

 

–

–

 





INH

52

 

7

 

H ← Remainder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EOR #opr

 

 

 

 

 

 

 

 

 

 

 

 

 

IMM

A8

ii

2

EOR opr

 

 

 

 

 

 

 

 

 

 

 

 

 

DIR

B8

dd

3

EOR opr

 

 

 

 

 

 

 

 

 

 

 

 

 

EXT

C8

hh ll

4

EOR opr,X

Exclusive OR M with A

 

A ← (A ⊕ M)

0

–

 

–



 



–

IX2

D8

ee ff

4

EOR opr,X

 

 

 

 

 

 

 

 

 

 

 

 

 

IX1

E8

ff

3

EOR ,X

 

 

 

 

 

 

 

 

 

 

 

 

 

IX

F8

 

2

EOR opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

SP1

9EE8

ff

4

EOR opr,SP

 

 

 

 

 

 

 

 

 

 

 

 

 

SP2

9ED8

ee ff

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INC opr

 

 

M ← (M) + 1

 

 

 

 

 

 

 

 

DIR

3C

dd

4

INCA

 

 

A ← (A) + 1

 

 

 

 

 

 

 

 

INH

4C

 

1

INCX

Increment

 

X ← (X) + 1



–

 

–



 



–

INH

5C

 

1

INC opr,X

 

M ← (M) + 1

 

 

IX1

6C

ff

4

INC ,X

 

 

M ← (M) + 1

 

 

 

 

 

 

 

 

IX

7C

 

3

INC opr,SP

 

 

M ← (M) + 1

 

 

 

 

 

 

 

 

SP1

9E6C

ff

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

86

Freescale Semiconductor

Page 85 Page 87
Page 86
Image 86
Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Instruction Set Summary Sheet 3, Dbnz opr,rel
Page 85 Page 87

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.
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