Dbnz opr,rel | Freescale Semiconductor MC68HC908MR32, MC68HC908MR16

Central Processor Unit (CPU)

Table 7-1. Instruction Set Summary (Sheet 3 of 6)

Effect

Address Mode

Opcode

Operand

Cycles

Source

Operation

Description

on CCR

Form

V

H

I

N

Z

C

CLR opr

M ← $00

DIR

3F

dd

3

CLRA

A ← $00

INH

4F

1

CLRX

X ← $00

INH

5F

1

CLRH

Clear

H ← $00

0

–

–

0

1

–

INH

8C

1

CLR opr,X

M ← $00

IX1

6F

ff

3

CLR ,X

M ← $00

IX

7F

2

CLR opr,SP

M ← $00

SP1

9E6F

ff

4

CMP #opr

IMM

A1

ii

2

CMP opr

DIR

B1

dd

3

CMP opr

EXT

C1

hh ll

4

CMP opr,X

Compare A with M

(A) – (M)

–

–

IX2

D1

ee ff

4

CMP opr,X

IX1

E1

ff

3

CMP ,X

IX

F1

2

CMP opr,SP

SP1

9EE1

ff

4

CMP opr,SP

SP2

9ED1

ee ff

5

COM opr

M ← (

) = $FF – (M)

DIR

33

dd

4

M

COMA

A

← (A) = $FF – (M)

INH

43

1

COMX

Complement (One’s Complement)

X

← (X) = $FF – (M)

0

–

–

1

INH

53

1

COM opr,X

M

← (M) = $FF – (M)

IX1

63

ff

4

COM ,X

M

← (M) = $FF – (M)

IX

73

3

COM opr,SP

M

← (M) = $FF – (M)

SP1

9E63

ff

5

CPHX #opr

Compare H:X with M

(H:X) – (M:M + 1)

–

–

IMM

65

ii ii+1

3

CPHX opr

DIR

75

dd

4

CPX #opr

IMM

A3

ii

2

CPX opr

DIR

B3

dd

3

CPX opr

EXT

C3

hh ll

4

CPX ,X

Compare X with M

(X) – (M)

–

–

IX2

D3

ee ff

4

CPX opr,X

IX1

E3

ff

3

CPX opr,X

IX

F3

2

CPX opr,SP

SP1

9EE3

ff

4

CPX opr,SP

SP2

9ED3

ee ff

5

DAA

Decimal Adjust A

(A)10

U

–

–

INH

72

2

A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1

5

DBNZ opr,rel

PC ← (PC) + 3 + rel ? (result) ≠ 0

DIR

3B

dd rr

3

DBNZA rel

PC ← (PC) + 2 + rel ? (result) ≠ 0

INH

4B

rr

3

DBNZX rel

Decrement and Branch if Not Zero

PC ← (PC) + 2 + rel ? (result) ≠ 0

–

–

–

–

–

–

INH

5B

rr

5

DBNZ opr,X,rel

PC ← (PC) + 3 + rel ? (result) ≠ 0

IX1

6B

ff rr

4

DBNZ X,rel

PC ← (PC) + 2 + rel ? (result) ≠ 0

IX

7B

rr

6

DBNZ opr,SP,rel

PC ← (PC) + 4 + rel ? (result) ≠ 0

SP1

9E6B

ff rr

DEC opr

M ← (M) – 1

DIR

3A

dd

4

DECA

A ← (A) – 1

INH

4A

1

DECX

Decrement

X ← (X) – 1

–

–

–

INH

5A

1

DEC opr,X

M ← (M) – 1

IX1

6A

ff

4

DEC ,X

M ← (M) – 1

IX

7A

3

DEC opr,SP

M ← (M) – 1

SP1

9E6A

ff

5

DIV

Divide

A ← (H:A)/(X)

–

–

–

–

INH

52

7

H ← Remainder

EOR #opr

IMM

A8

ii

2

EOR opr

DIR

B8

dd

3

EOR opr

EXT

C8

hh ll

4

EOR opr,X

Exclusive OR M with A

A ← (A ⊕ M)

0

–

–

–

IX2

D8

ee ff

4

EOR opr,X

IX1

E8

ff

3

EOR ,X

IX

F8

2

EOR opr,SP

SP1

9EE8

ff

4

EOR opr,SP

SP2

9ED8

ee ff

5

INC opr

M ← (M) + 1

DIR

3C

dd

4

INCA

A ← (A) + 1

INH

4C

1

INCX

Increment

X ← (X) + 1

–

–

–

INH

5C

1

INC opr,X

M ← (M) + 1

IX1

6C

ff

4

INC ,X

M ← (M) + 1

IX

7C

3

INC opr,SP

M ← (M) + 1

SP1

9E6C

ff

5

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

86	Freescale Semiconductor

Image 86

Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual Instruction Set Summary Sheet 3, Dbnz opr,rel

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.

Contents

MC68HC908MR32 MC68HC908MR16 Page MC68HC908MR32 MC68HC908MR16 Data SheetMC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Date Revision Description Level Numbers Revision HistoryRevision History List of Chapters List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Table of Contents Chapter Clock Generator Module CGM Table of ContentsChapter Analog-to-Digital Converter ADC Chapter Configuration Register Config Chapter Computer Operating Properly COP Chapter Low-Voltage Inhibit LVI Chapter Central Processor Unit CPUChapter External Interrupt IRQ Chapter Pulse-Width Modulator for Motor Control Pwmmc Chapter Power-On Reset PORChapter Input/Output I/O Ports Ports Chapter Serial Communications Interface Module SCI Chapter System Integration Module SIM Chapter Serial Peripheral Interface Module SPI Chapter Timer Interface a Tima Chapter Timer Interface B Timb Chapter Development Support Chapter Electrical Specifications Chapter Ordering Information and Mechanical Specifications Introduction FeaturesChapter General Description MCU Block Diagram General Description Diagram MCU Block Pin Assignments Pin QFP Pin Assignments Pin Sdip Pin Assignments Pin Assignments External Reset Pin RST Power Supply Pins VDD and VSSOscillator Pins OSC1 and OSC2 CGM Power Supply Pins Vdda and Vssad Port B I/O Pins PTB7/ATD7-PTB0/ATD0 Analog Power Supply Pins Vddad and VssadPort a Input/Output I/O Pins PTA7-PTA0 Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8 Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK PWM Ground Pin Pwmgnd Reserved Memory Locations Chapter MemoryUnimplemented Memory Locations Memory I/O SectionMemory Map MC68HC908MR32 Memory Map Memory Map Control, Status, and Data Registers Summary Sheet 1 Memory Addr Control, Status, and Data Registers Summary Sheet 2 Memory Map Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 3 Memory Addr Register Name Control, Status, and Data Registers Summary Sheet 4 Control, Status, and Data Registers Summary Sheet 5 Memory Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 6 Addr Register Name Control, Status, and Data Registers Summary Sheet 7 Control, Status, and Data Registers Summary Sheet 8 Vector Addresses Address Vector Low Monitor ROM Random-Access Memory RAMMonitor ROM Address Vector Flash Memory Flash Flash Control Register Mass Mass Erase Control Bit Hven High-Voltage Enable BitFlash Page Erase Operation Erase Erase Control Bit Flash Mass Erase Operation Flash Program Operation Only bytes which are currently $FF may be programmed Flash Programming Flowchart Flash Block Protection Flash Block Protect Register Examples of Protect Start Address Wait ModeStop Mode Chapter Analog-to-Digital Converter ADC Functional Description Block Diagram Highlighting ADC Block and Pins Analog-to-Digital Converter ADC Functional Description ADC Port I/O PinsVoltage Conversion Result Justification Conversion TimeContinuous Conversion Bit Truncation Mode Error Monotonicity Interrupts Wait ModeI/O Signals ADC External Connections I/O RegistersADC Voltage In Advin 6.2 ANx Aien ADC Interrupt Enable Bit ADC Status and Control Register Mux Channel Select Input Select ADC Data Register High ADC Data Register Low ADC Clock Rate ADC Clock RegisterADC Clock Divide Ratio Analog-to-Digital Converter ADC Chapter Clock Generator Module CGM Cgmvclk CGM Block Diagram Clock Generator Module CGM PLL Circuits Phase-Locked Loop Circuit PLLCrystal Oscillator Circuit Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Variable Definition Programming the PLLVariable Definitions Base Clock Selector Circuit Special Programming Exceptions CGM External Connections CGM External Connections Crystal Amplifier Input Pin OSC1 PLL Analog Power Pin VddaOscillator Enable Signal Simoscen Crystal Amplifier Output Pin OSC2 CGM Base Clock Output Cgmout Crystal Output Frequency Signal CgmxclkCGM Registers CGM CPU Interrupt Cgmint Pllon PLL On Bit PLL Control RegisterPllf PLL Interrupt Flag BCS Base Clock Select Bit PLL Bandwidth Control Register Lock Lock Indicator BitACQ Acquisition Mode Bit PCTL30 Unimplemented Bits PBWC30 Reserved for Test PLL Programming RegisterXLD Crystal Loss Detect Bit VCO Frequency Multiplier N Selection VRS74 VCO Range Select Bits Interrupts Parametric Influences on Reaction Time Acquisition/Lock Time SpecificationsAcquisition/Lock Time Definitions Reaction Time Calculation Acquisition/Lock Time SpecificationsChoosing a Filter Capacitor Frequency Chapter Configuration Register Config Configuration Register COP Block Diagram Chapter Computer Operating Properly COP Reset Vector Fetch Power-On ResetInternal Reset Copctl Write Copd COP Disable Monitor ModeStop Mode COP Control Register Freescale Semiconductor Chapter Central Processor Unit CPU CPU Registers Central Processor Unit CPU AccumulatorIndex Register CPU Registers Stack PointerProgram Counter Interrupt Mask Condition Code RegisterHalf-Carry Flag Negative Flag CPU During Break Interrupts Low-Power ModesArithmetic/Logic Unit ALU Zero Flag Instruction Set Summary Instruction Set Summary Sheet 1 Source Operation Description On CCR Form Instruction Set Summary Sheet 2Instruction Set Summary Instruction Set Summary Sheet 3 Dbnz opr,rel Instruction Set Summary Sheet 4 JMP ,X Instruction Set Summary Sheet 5 Operation Description On CCR Form Opcode Map Opcode MapInstruction Set Summary Sheet 6 Opcode Map 9ED 9EE IRQ Module Block Diagram Chapter External Interrupt IRQ IRQ Pin External Interrupt IRQ IRQ Interrupt Flowchart IRQ Pin IRQ Status and Control Register IRQ Status and Control Register Iscr Irqf IRQ Flag IRQ Status and Control Register Freescale Semiconductor LVI Module Block Diagram Chapter Low-Voltage Inhibit LVI Polled LVI Operation Forced Reset OperationFalse Reset Protection LVI Trip Selection Lviout Bit Indication LVI Status and Control RegisterLVI Interrupts LVI Status and Control Register 100 Freescale Semiconductor Chapter Input/Output I/O Ports Ports I/O Port Register Summary Input/Output I/O Ports Ports Addr Register Name Data Direction Register a Port aPort a Data Register Port a Port a Pin Functions Port BPort B Data Register Input/Output I/O Ports Ports Port B Data Direction Register BPort B Pin Functions Data Direction Register C Port CPort C Data Register Port D Port DPort C Pin Functions PTC60 Port E Data Register PTD Bit Pin Mode Accesses to PTD ReadPort E Port D Pin Functions Port E Pin Functions Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTEData Direction Register E Port E Data Direction Register F Port FPort F Data Register Port F Pin Functions Port F 112 Freescale Semiconductor Chapter Power-On Reset POR 114 Freescale Semiconductor Chapter Pulse-Width Modulator for Motor Control Pwmmc Block Diagram Highlighting Pwmmc Block and Pins Pulse-Width Modulator for Motor Control Pwmmc PWM Module Block Diagram Features Register Summary Sheet 2 Features Addr Register Name Bit Register Summary Sheet 3 Resolution Timebase Edge-Aligned PWM Positive Polarity Timebase Load Operation PWM GeneratorsPrescaler PWM Prescaler Reload Frequency Change PWM Interrupt Requests Center-Aligned PWM Value Loading PWMVALxHPWMVALxL Condition PWM Value Used PWM Data Overflow and Underflow ConditionsPWM Data Overflow and Underflow Conditions 12. Complementary Pairing Output Control Dead-Time Insertion Output Control 14. Dead-Time Generators 15. Effects of Dead-Time Insertion 17. Dead-Time and Small Pulse Widths Current Sense Pins Current Voltage On Current Correction Methods Current Correction Bits Correction Method ISENS1 and ISENS0 Output Polarity 20. Top/Bottom Correction for PWMs 1 21. PWM Polarity OUTx Bits OUTx Bit Complementary Mode Independent ModePWM Output Port Control 23. Dead-Time Insertion During Outctl = Fault Protection Fault ProtectionFault Condition Input Pins 26. PWM Disabling Scheme Fault Pin Filter Automatic Mode 28. PWM Disabling in Automatic Mode Manual Mode Software Output Disable Output Port Control 32. Pwmen and PWM Pins Initialization and the Pwmen Bit Control Logic Block PWM Operation in Wait ModePWM Operation in Wait Mode PWM Counter Registers PWM Counter Modulo Registers 35. PWM Counter Modulo Register High Pmodh PWMx Value Registers Control Logic Block PWM Control Register Disy Software Disable Bit for Bank Y BitPwmint PWM Interrupt Enable Bit Pwmf PWM Reload Flag Pwmen PWM Module Enable Bit LDOK- Load OK Bit IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1 PRSC1 and PRSC0 PWM Prescaler Bits IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5 Dead-Time Write-Once Register PWM Disable Mapping Write-Once RegisterFault Control Register FINT1 Fault 1 Interrupt Enable Bit FINT3 Fault 3 Interrupt Enable BitFINT2 Fault 2 Interrupt Enable Bit Fault Status Register Fault Acknowledge Register DT1 Dead-Time 1 Bit PWM Output Control RegisterDT2 Dead-Time 2 Bit 10. OUTx Bits PWM Glossary PWM Glossary 48. PWM Load Cycle/Frequency Definition Chapter Serial Communications Interface Module SCI Block Diagram Highlighting SCI Block and Pins Serial Communications Interface Module SCI SCI Module Block Diagram Data Format Serial Communications Interface Module SCI Addr Transmitter SCI Transmitter Break Characters Character LengthCharacter Transmission Inversion of Transmitted Output ReceiverIdle Characters Transmitter Interrupts SCI Receiver Block Diagram Character Reception Data Sampling Start Bit Verification Data Bit RecoveryStop Bit Recovery Receiver Wakeup Framing ErrorsError Interrupts Receiver Interrupts 13.6.1 PTF5/TxD Transmit Data 13.6 I/O SignalsSCI During Break Module Interrupts SCI Control Register 13.7 I/O Registers13.6.2 PTF4/RxD Receive Data PEN Parity Enable Bit Ensci Enable SCI BitMode Character Length Bit Txinv Transmit Inversion Bit Control Bits Character Format Tcie Transmission Complete Interrupt Enable BitCharacter Format Selection Start Data Parity Stop TE Transmitter Enable Bit Scrie SCI Receive Interrupt Enable BitIlie Idle Line Interrupt Enable Bit RE Receiver Enable Bit Feie Receiver Framing Error Interrupt Enable Bit Orie Receiver Overrun Interrupt Enable BitNeie Receiver Noise Error Interrupt Enable Bit Peie Receiver Parity Error Interrupt Enable Bit Scrf SCI Receiver Full Bit SCI Status RegisterTC Transmission Complete Bit Idle Receiver Idle Bit Or Receiver Overrun Bit NF Receiver Noise Flag Bit FE Receiver Framing Error BitPE Receiver Parity Error Bit RPF -Reception-in-Progress Flag SCI Data RegisterSCI Baud Rate Register SCI Baud Rate Prescaling SCI Baud Rate Selection Baud Rate Divisor BD SCI Baud Rate Selection Examples Baud Rate Divisor PD Divisor BD 180 Freescale Semiconductor Chapter System Integration Module SIM Signal Name ConventionsSignal Name Description Bus Timing Clock Startup from POR or LVI ResetSIM Bus Clock Control and Generation System Integration Module SIM External Pin Reset Reset and System InitializationClocks in Wait Mode Reset and System Initialization PIN Bit Set Timing Active Resets from Internal SourcesReset Type Number of Cycles Required to Set PIN Power-On Reset POR Computer Operating Properly COP Reset SIM Counter SIM Counter During Power-On ResetSIM Counter and Reset States Exception Control Exception ControlInterrupts Interrupt Processing Interrupt Recovery Hardware Interrupts Software Interrupt SWI Instruction Low-Power ModeReset SIM Registers SIM RegistersSIM Break Status Register Ilop Illegal Opcode Reset Bit SIM Reset Status RegisterPIN External Reset Bit Ilad Illegal Address Reset Bit opcode fetches only SIM Break Flag Control Register 194 Freescale Semiconductor Pin Name Conventions Chapter Serial Peripheral Interface Module SPIPin Name Conventions Block Diagram Highlighting SPI Block and Pins Serial Peripheral Interface Module SPI SPI Module Block Diagram Master Mode Serial Peripheral Interface Module SPI Addr Transmission Formats Slave ModeClock Phase and Polarity Controls Transmission Formats Transmission Format When Cpha = Transmission Format Cpha = Transmission Initiation Latency Transmission Start Delay Master Error Conditions Error ConditionsOverflow Error Mode Fault Error 10. Clearing Sprf When Ovrf Interrupt Is Not Enabled Freescale Semiconductor 205 SPI Interrupts Flag Request Queuing Transmission Data Resetting the SPIResetting the SPI 15.11 I/O Signals 12. SPRF/SPTE CPU Interrupt Timing Mosi Master Out/Slave SignalsMiso Master In/Slave Out Spsck Serial Clock 15.12 I/O Registers SPI ConfigurationSPI Configuration State of SS Logic VSS Clock Ground Spmstr SPI Master Bit Cpha Clock Phase BitSpwom SPI Wired-OR Mode Bit Cpol Clock Polarity Bit Errie Error Interrupt Enable Bit SPE SPI Enable BitSPTIE- SPI Transmit Interrupt Enable Bit SPI Status and Control Register Ovrf Overflow Bit Modf Mode Fault BitModfen Mode Fault Enable Bit Spte SPI Transmitter Empty Bit SPI Data Register SPI Master Baud Rate Selection Chapter Timer Interface a Tima 2is a block diagram of the Tima Block Diagram Highlighting Tima Block and Pins Timer Interface a Tima Tima Block Diagram Timer Interface a Tima Addr Register Name Bit TIM I/O Register Summary Tima Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Pulse-Width Modulation PWM Buffered Output Compare Unbuffered PWM Signal Generation PWM Period and Pulse Width Buffered PWM Signal Generation PWM Initialization 224 Freescale Semiconductor 16.7 I/O Registers 16.6 I/O SignalsTima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A Tima Clock Pin PTE3/TCLKA Tstop Tima Stop Bit Toie Tima Overflow Interrupt Enable BitTrst Tima Reset Bit Prescaler Selection Tima Counter RegistersPS20 Prescaler Select Bits PS20 Tima Clock Source Tima Counter Modulo Registers Tima Channel Status and Control Registers CHxIE Channel x Interrupt Enable Bit ELSxB and ELSxA Edge/Level Select Bits MSxB Mode Select Bit BMSxA Mode Select Bit a TOVx Toggle-On-Overflow Bit MSxBMSxA ELSxBELSxA Mode ConfigurationMode, Edge, and Level Selection CHxMAX Channel x Maximum Duty Cycle Bit Tima Channel Registers 10. Tima Channel Registers 10. Tima Channel Registers TACH0H/L-TACH3H/L 234 Freescale Semiconductor Chapter Timer Interface B Timb Timb module is not available in the 56-pin Sdip Block Diagram Highlighting Timb Block and Pins Timer Interface B Timb Timb Block Diagram Timer Interface B Timb Addr Register Name Bit Timb Counter Prescaler Freescale Semiconductor 239 240 Freescale Semiconductor Freescale Semiconductor 241 242 Freescale Semiconductor Timb Clock Pin PTE0/TCLKB 17.6 I/O SignalsTimb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1B Timb Status and Control Register Toie Timb Overflow Interrupt Enable Bit17.7 I/O Registers PS20 Timb Clock Source Trst Timb Reset BitTstop Timb Stop Bit Timb Counter Registers Timb Counter Modulo Registers Timb Channel Status and Control Registers 248 Freescale Semiconductor PWM Timb Channel Registers 10. Timb Channel Registers TBCH0H/L-TBCH1H/L Functional Description Chapter Development SupportBreak Module BRK Flag Protection During Break Interrupts Break Module Block Diagram Development Support Low-Power Modes Break Module Registers Break Address Registers Break Status and Control RegisterBrka Break Active Bit Break Flag Control Register Monitor ROM MONBreak Status Register Monitor ROM MON Normal Monitor Mode Entering Monitor ModeMode Differences Monitor Mode Circuit Monitor Mode Signal Requirements and Options $FFFF Forced Monitor Mode Data Format Echoing Break SignalCommands Iread Indexed Read Command Read Read Memory CommandWrite Write Memory Command Command Sequence RUN Run User Program Command Iwrite Indexed Write CommandReadsp Read Stack Pointer Command Monitor Baud Rate Selection SecurityBaud Rate 13. Monitor Mode Entry Timing Absolute Maximum Ratings Chapter Electrical SpecificationsCharacteristic1 Symbol Value Unit Characteristic Symbol Value Unit Thermal CharacteristicsElectrical Specifications Functional Operating Range Characteristic1 Symbol Min Typ2 Max Unit DC Electrical CharacteristicsDC Electrical Characteristics Characteristic Symbol Min Max Unit Flash Memory CharacteristicsCharacteristic Symbol Min Typ Max Unit Control Timing Diagram Characteristic2 Symbol Min Max Unit Number1 Serial Peripheral Interface CharacteristicsSerial Peripheral Interface Characteristics SPI Master Timing SPI Slave Timing Characteristic Symbol Min Typ Max TImer Interface Module CharacteristicsClock Generation Module Component Specifications CGM Operating Conditions Description Symbol Min Typ Max CGM Acquisition/Lock Time SpecificationsCGM Acquisition/Lock Time Specifications Analog-to-Digital Converter ADC Characteristics 3FF Order Numbers Chapter Ordering Information and Mechanical SpecificationsOrder Numbers MC Order Number Operating Ordering Information and Mechanical Specifications 20.3 64-Pin Plastic Quad Flat Pack QFP 20.4 56-Pin Shrink Dual In-Line Package Sdip Pin Shrink Dual In-Line Package Sdip 278 Freescale Semiconductor Appendix a MC68HC908MR16 Figure A-1. MC68HC908MR16 Memory Map MC68HC908MR16Page How to Reach Us