Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 - page 56

Analog-to-Digital Converter (ADC)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
56 Freescale Semiconductor
ADICLK — ADC Input Clock Select Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at fADIC, correct operation can be guaranteed. See
19.13 Analog-to-Digital Converter (ADC) Characteristics.
1 = Internal bus clock
0 = External clock, CGMXCLK
MODE1:MODE0 — Modes of Result Justification Bits
MODE1:MODE0 selects among four modes of operation. The manner in which the ADC conversion
results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns
right-justified mode.
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified sign data mode
CGMXCLK or bus frequency
fADIC = ADIV[2:0]