Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 9.3.1 Polled LVI Operation, 9.3.2 Forced Reset Operation, 9.3.3 False Reset Protection, 9.3.4 LVI Trip Selection

Low-Voltage Inhibit (LVI)

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

98 Freescale Semiconductor

Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VLVRX + VLVHX.

VDDmust be above VLVRX + VLVHX for only one CPU cycle to bring the MCU out of reset. See

14.3.2.6 Low-Voltage Inhibit (LVI) Reset. The output of the comparator controls the state of the LVIOUT

flag in the LVI status register (LVISCR).

An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.

See 19.5 DC Electrical Characteristics.

9.3.1 Polled LVI Operation

In applications that can operate at VDD levels below VLVRX, software can monitor VDD by polling the

LVIOUT bit. In the configuration register, the LVIPWR bit must be 1 to enable the LVI module, and the

LVIRST bit must be 0 to disable LVI resets. See Chapter 5 Configuration Register (CONFIG). TRPSEL

in the LVISCR selects VLVRX.

9.3.2 Forced Reset Operation

In applications that require VDD to remain above VLVRX, enabling LVI resets allows the LVI module to

reset the MCU when VDD falls to the VLVRX level and remains at or below that level for nine or more

consecutive CPU cycles. In the CONFIG register, the LVIPWR and LVIRST bits must be 1s to enable the

LVI module and to enable LVI resets. TRPSEL in the LVISCR selects VLVRX.

9.3.3 False Reset Protection

The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI

module to reset the MCU, VDD must remain at or below VLVRX for nine or more consecutive CPU cycles.

VDD must be above VLVRX + VLVHX for only one CPU cycle to bring the MCU out of reset. TRPSEL in the

LVISCR selects VLVRX + VLVHX.

9.3.4 LVI Trip Selection

The TRPSEL bit allows the user to chose between 5 percent and 10percent tolerance when monitoring

the supply voltage. The 10 percent option is enabled out of reset. Writing a 1 to TRPSEL will enable 5

percent option.

NOTE

The microcontroller is guaranteed to operate at a minimum supply voltage.

The trip point (VLVR1 or VLVR2) may be lower than this. See 19.5 DC

Electrical Characteristics.

Addr. Register Name Bit 7654321Bit 0

$FE0F

LVI Status and Control Register

(LVISCR)

See page 99.

Read: LVIOUT 0

TRPSEL

00000

Write:RR RRRRR

Reset:00000000

R=Reserved

Figure 9-2. LVI I/O Register Summary