SCI Module Block Diagram | Freescale Semiconductor MC68HC908MR16

Functional Description

13.3 Functional Description

Figure 13-2shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.

INTERNAL BUS


			SCI DATA
			REGISTER						TRANSMITTER INTERRUPT CONTROL


PTF4/RxD			RECEIVE
			RECEIVE
			SHIFT REGISTER
			SHIFT REGISTER

SCTIE

TCIE

SCRIE

ILIE

TE

SCTE

RE

TC

RWU

SCRF

SBK

IDLE


	WAKEUP				RECEIVE
	CONTROL				CONTROL

			ENSCI
	fOP	⎟ 4	PRE-	BAUD RATE
	fOP	⎟ 4	SCALER	GENERATOR
			SCALER	GENERATOR
				⎟ 16

SCI DATA

REGISTER

RECEIVER INTERRUPT CONTROL

ERROR INTERRUPT CONTROL

TRANSMIT

SHIFT REGISTER

TXINV

R8

T8

OR

ORIE

NF

NEIE

FE

FEIE

PE

PEIE

LOOPS

LOOPS

ENSCI

FLAG

TRANSMIT

CONTROL

CONTROL

M

BKF

WAKE

RPF

ILTY

PEN

PTY

DATA SELECTION

CONTROL

PTF5/TxD

Figure 13-2. SCI Module Block Diagram

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

159

Image 159

Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual SCI Module Block Diagram

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

One of the standout features of the MC68HC908MR series is its CMOS technology, which enhances performance while minimizing power consumption. This makes these microcontrollers suitable for battery-operated devices. They operate at a maximum clock frequency of 2 MHz and offer a 16-bit architecture, providing a solid balance between processing power and efficiency.

The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

Another significant characteristic of these microcontrollers is their integrated peripherals. They come with multiple input/output (I/O) pins, which allow for connectivity with various sensors and actuators. The built-in timer systems offer precise timing control for automotive and industrial applications, while the Analog-to-Digital Converter (ADC) provides essential conversion capabilities for various analog signals.

For communication purposes, the MC68HC908MR series includes a serial communication interface, enabling easy integration with other devices and systems. This versatility facilitates the development of complex systems that require interaction with external components.

Security is another crucial aspect of these microcontrollers. They have built-in fail-safe mechanisms to ensure reliable operation under various conditions, making them suitable for critical systems. Additionally, their robust architecture helps to safeguard against potential disruptions or attacks.

In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.

Contents

MC68HC908MR32 MC68HC908MR16 Page Data Sheet MC68HC908MR32 MC68HC908MR16 Data Sheet, RevMC68HC908MR32 MC68HC908MR16 Revision History Revision HistoryDate Revision Description Level Numbers List of Chapters List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev Table of Contents Table of Contents Chapter Analog-to-Digital Converter ADCChapter Clock Generator Module CGM Chapter Computer Operating Properly COP Chapter Configuration Register Config Chapter Central Processor Unit CPU Chapter External Interrupt IRQChapter Low-Voltage Inhibit LVI Chapter Power-On Reset POR Chapter Input/Output I/O Ports PortsChapter Pulse-Width Modulator for Motor Control Pwmmc Chapter Serial Communications Interface Module SCI Chapter Serial Peripheral Interface Module SPI Chapter System Integration Module SIM Chapter Timer Interface a Tima Chapter Development Support Chapter Timer Interface B Timb Chapter Ordering Information and Mechanical Specifications Chapter Electrical Specifications Features Chapter General DescriptionIntroduction General Description MCU Block Diagram MCU Block Diagram Pin QFP Pin Assignments Pin Assignments Pin Assignments Pin Sdip Pin Assignments CGM Power Supply Pins Vdda and Vssad Power Supply Pins VDD and VSSOscillator Pins OSC1 and OSC2 External Reset Pin RST Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8 Analog Power Supply Pins Vddad and VssadPort a Input/Output I/O Pins PTA7-PTA0 Port B I/O Pins PTB7/ATD7-PTB0/ATD0 PWM Ground Pin Pwmgnd Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK Chapter Memory Unimplemented Memory LocationsReserved Memory Locations I/O Section Memory MapMemory Memory Map MC68HC908MR32 Memory Map Memory Addr Control, Status, and Data Registers Summary Sheet 1 Memory Map Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 2 Memory Addr Register Name Control, Status, and Data Registers Summary Sheet 3 Control, Status, and Data Registers Summary Sheet 4 Memory Addr Register Name Bit Control, Status, and Data Registers Summary Sheet 5 Addr Register Name Control, Status, and Data Registers Summary Sheet 6 Control, Status, and Data Registers Summary Sheet 7 Control, Status, and Data Registers Summary Sheet 8 Address Vector Low Vector Addresses Address Vector Random-Access Memory RAMMonitor ROM Monitor ROM Flash Control Register Flash Memory Flash Erase Erase Control Bit Hven High-Voltage Enable BitFlash Page Erase Operation Mass Mass Erase Control Bit Flash Mass Erase Operation Only bytes which are currently $FF may be programmed Flash Program Operation Flash Programming Flowchart Flash Block Protect Register Flash Block Protection Wait Mode Stop ModeExamples of Protect Start Address Functional Description Chapter Analog-to-Digital Converter ADC Analog-to-Digital Converter ADC Block Diagram Highlighting ADC Block and Pins ADC Port I/O Pins Voltage ConversionFunctional Description Conversion Time Continuous ConversionResult Justification Monotonicity Bit Truncation Mode Error Wait Mode I/O SignalsInterrupts 6.2 ANx I/O RegistersADC Voltage In Advin ADC External Connections ADC Status and Control Register Aien ADC Interrupt Enable Bit Input Select Mux Channel Select ADC Data Register Low ADC Data Register High ADC Clock Register ADC Clock Divide RatioADC Clock Rate Analog-to-Digital Converter ADC Cgmvclk Chapter Clock Generator Module CGM Clock Generator Module CGM CGM Block Diagram Phase-Locked Loop Circuit PLL Crystal Oscillator CircuitPLL Circuits Manual and Automatic PLL Bandwidth Modes Acquisition and Tracking Modes Programming the PLL Variable DefinitionsVariable Definition Special Programming Exceptions Base Clock Selector Circuit CGM External Connections CGM External Connections Crystal Amplifier Output Pin OSC2 PLL Analog Power Pin VddaOscillator Enable Signal Simoscen Crystal Amplifier Input Pin OSC1 CGM CPU Interrupt Cgmint Crystal Output Frequency Signal CgmxclkCGM Registers CGM Base Clock Output Cgmout BCS Base Clock Select Bit PLL Control RegisterPllf PLL Interrupt Flag Pllon PLL On Bit PCTL30 Unimplemented Bits Lock Lock Indicator BitACQ Acquisition Mode Bit PLL Bandwidth Control Register VCO Frequency Multiplier N Selection PLL Programming RegisterXLD Crystal Loss Detect Bit PBWC30 Reserved for Test Interrupts VRS74 VCO Range Select Bits Acquisition/Lock Time Specifications Acquisition/Lock Time DefinitionsParametric Influences on Reaction Time Acquisition/Lock Time Specifications Choosing a Filter CapacitorReaction Time Calculation Frequency Chapter Configuration Register Config Configuration Register Chapter Computer Operating Properly COP COP Block Diagram Copctl Write Power-On ResetInternal Reset Reset Vector Fetch COP Control Register Monitor ModeStop Mode Copd COP Disable Freescale Semiconductor CPU Registers Chapter Central Processor Unit CPU Accumulator Index RegisterCentral Processor Unit CPU Stack Pointer Program CounterCPU Registers Negative Flag Condition Code RegisterHalf-Carry Flag Interrupt Mask Zero Flag Low-Power ModesArithmetic/Logic Unit ALU CPU During Break Interrupts Instruction Set Summary Sheet 1 Instruction Set Summary Instruction Set Summary Sheet 2 Instruction Set SummarySource Operation Description On CCR Form Dbnz opr,rel Instruction Set Summary Sheet 3 JMP ,X Instruction Set Summary Sheet 4 Operation Description On CCR Form Instruction Set Summary Sheet 5 Opcode Map Instruction Set Summary Sheet 6Opcode Map 9ED 9EE Opcode Map Chapter External Interrupt IRQ IRQ Module Block Diagram External Interrupt IRQ IRQ Pin IRQ Pin IRQ Interrupt Flowchart IRQ Status and Control Register Iscr IRQ Status and Control Register IRQ Status and Control Register Irqf IRQ Flag Freescale Semiconductor Chapter Low-Voltage Inhibit LVI LVI Module Block Diagram LVI Trip Selection Forced Reset OperationFalse Reset Protection Polled LVI Operation LVI Status and Control Register LVI Status and Control RegisterLVI Interrupts Lviout Bit Indication 100 Freescale Semiconductor I/O Port Register Summary Chapter Input/Output I/O Ports Ports Input/Output I/O Ports Ports Addr Register Name Port a Port aPort a Data Register Data Direction Register a Input/Output I/O Ports Ports Port BPort B Data Register Port a Pin Functions Data Direction Register B Port B Pin FunctionsPort B Port C Port C Data RegisterData Direction Register C PTC60 Port DPort C Pin Functions Port D Port D Pin Functions PTD Bit Pin Mode Accesses to PTD ReadPort E Port E Data Register Port E Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTEData Direction Register E Port E Pin Functions Port F Port F Data RegisterData Direction Register F Port F Port F Pin Functions 112 Freescale Semiconductor Chapter Power-On Reset POR 114 Freescale Semiconductor Chapter Pulse-Width Modulator for Motor Control Pwmmc Pulse-Width Modulator for Motor Control Pwmmc Block Diagram Highlighting Pwmmc Block and Pins Features PWM Module Block Diagram Register Summary Sheet 2 Register Summary Sheet 3 Features Addr Register Name Bit Timebase Resolution Timebase Edge-Aligned PWM Positive Polarity PWM Prescaler PWM GeneratorsPrescaler Load Operation PWM Interrupt Requests Reload Frequency Change Center-Aligned PWM Value Loading PWM Data Overflow and Underflow Conditions PWM Data Overflow and Underflow ConditionsPWMVALxHPWMVALxL Condition PWM Value Used Output Control 12. Complementary Pairing Output Control Dead-Time Insertion 14. Dead-Time Generators 15. Effects of Dead-Time Insertion 17. Dead-Time and Small Pulse Widths Current Voltage On Current Current Sense Pins Current Correction Bits Correction Method ISENS1 and ISENS0 Correction Methods 20. Top/Bottom Correction for PWMs 1 Output Polarity 21. PWM Polarity OUTx Bit Complementary Mode Independent Mode PWM Output Port ControlOUTx Bits 23. Dead-Time Insertion During Outctl = Fault Protection Fault Condition Input PinsFault Protection 26. PWM Disabling Scheme Automatic Mode Fault Pin Filter Manual Mode 28. PWM Disabling in Automatic Mode Output Port Control Software Output Disable Initialization and the Pwmen Bit 32. Pwmen and PWM Pins PWM Counter Registers PWM Operation in Wait ModePWM Operation in Wait Mode Control Logic Block 35. PWM Counter Modulo Register High Pmodh PWM Counter Modulo Registers Control Logic Block PWMx Value Registers Pwmf PWM Reload Flag Disy Software Disable Bit for Bank Y BitPwmint PWM Interrupt Enable Bit PWM Control Register LDOK- Load OK Bit Pwmen PWM Module Enable Bit IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1 IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3 IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5PRSC1 and PRSC0 PWM Prescaler Bits PWM Disable Mapping Write-Once Register Fault Control RegisterDead-Time Write-Once Register FINT3 Fault 3 Interrupt Enable Bit FINT2 Fault 2 Interrupt Enable BitFINT1 Fault 1 Interrupt Enable Bit Fault Status Register Fault Acknowledge Register 10. OUTx Bits PWM Output Control RegisterDT2 Dead-Time 2 Bit DT1 Dead-Time 1 Bit PWM Glossary PWM Glossary 48. PWM Load Cycle/Frequency Definition Chapter Serial Communications Interface Module SCI Serial Communications Interface Module SCI Block Diagram Highlighting SCI Block and Pins SCI Module Block Diagram Serial Communications Interface Module SCI Addr Data Format SCI Transmitter Transmitter Character Length Character TransmissionBreak Characters Transmitter Interrupts ReceiverIdle Characters Inversion of Transmitted Output SCI Receiver Block Diagram Data Sampling Character Reception Data Bit Recovery Stop Bit RecoveryStart Bit Verification Receiver Interrupts Framing ErrorsError Interrupts Receiver Wakeup 13.6 I/O Signals SCI During Break Module Interrupts13.6.1 PTF5/TxD Transmit Data 13.7 I/O Registers 13.6.2 PTF4/RxD Receive DataSCI Control Register Txinv Transmit Inversion Bit Ensci Enable SCI BitMode Character Length Bit PEN Parity Enable Bit Start Data Parity Stop Tcie Transmission Complete Interrupt Enable BitCharacter Format Selection Control Bits Character Format RE Receiver Enable Bit Scrie SCI Receive Interrupt Enable BitIlie Idle Line Interrupt Enable Bit TE Transmitter Enable Bit Peie Receiver Parity Error Interrupt Enable Bit Orie Receiver Overrun Interrupt Enable BitNeie Receiver Noise Error Interrupt Enable Bit Feie Receiver Framing Error Interrupt Enable Bit SCI Status Register TC Transmission Complete BitScrf SCI Receiver Full Bit Or Receiver Overrun Bit Idle Receiver Idle Bit FE Receiver Framing Error Bit PE Receiver Parity Error BitNF Receiver Noise Flag Bit SCI Baud Rate Prescaling SCI Data RegisterSCI Baud Rate Register RPF -Reception-in-Progress Flag Baud Rate Divisor BD SCI Baud Rate Selection Baud Rate Divisor PD Divisor BD SCI Baud Rate Selection Examples 180 Freescale Semiconductor Signal Name Conventions Signal Name DescriptionChapter System Integration Module SIM System Integration Module SIM Clock Startup from POR or LVI ResetSIM Bus Clock Control and Generation Bus Timing Reset and System Initialization Reset and System InitializationClocks in Wait Mode External Pin Reset Active Resets from Internal Sources Reset Type Number of Cycles Required to Set PINPIN Bit Set Timing Computer Operating Properly COP Reset Power-On Reset POR SIM Counter During Power-On Reset SIM Counter and Reset StatesSIM Counter Exception Control InterruptsException Control Interrupt Processing Hardware Interrupts Interrupt Recovery Low-Power Mode ResetSoftware Interrupt SWI Instruction SIM Registers SIM Break Status RegisterSIM Registers Ilad Illegal Address Reset Bit opcode fetches only SIM Reset Status RegisterPIN External Reset Bit Ilop Illegal Opcode Reset Bit SIM Break Flag Control Register 194 Freescale Semiconductor Chapter Serial Peripheral Interface Module SPI Pin Name ConventionsPin Name Conventions Serial Peripheral Interface Module SPI Block Diagram Highlighting SPI Block and Pins SPI Module Block Diagram Serial Peripheral Interface Module SPI Addr Master Mode Transmission Formats Slave ModeClock Phase and Polarity Controls Transmission Formats Transmission Format Cpha = Transmission Format When Cpha = Transmission Initiation Latency Transmission Start Delay Master Error Conditions Overflow ErrorError Conditions 10. Clearing Sprf When Ovrf Interrupt Is Not Enabled Mode Fault Error Freescale Semiconductor 205 Flag Request SPI Interrupts Resetting the SPI Resetting the SPIQueuing Transmission Data 12. SPRF/SPTE CPU Interrupt Timing 15.11 I/O Signals Spsck Serial Clock SignalsMiso Master In/Slave Out Mosi Master Out/Slave VSS Clock Ground SPI ConfigurationSPI Configuration State of SS Logic 15.12 I/O Registers Cpol Clock Polarity Bit Cpha Clock Phase BitSpwom SPI Wired-OR Mode Bit Spmstr SPI Master Bit SPI Status and Control Register SPE SPI Enable BitSPTIE- SPI Transmit Interrupt Enable Bit Errie Error Interrupt Enable Bit Spte SPI Transmitter Empty Bit Modf Mode Fault BitModfen Mode Fault Enable Bit Ovrf Overflow Bit SPI Master Baud Rate Selection SPI Data Register 2is a block diagram of the Tima Chapter Timer Interface a Tima Timer Interface a Tima Block Diagram Highlighting Tima Block and Pins Tima Block Diagram TIM I/O Register Summary Timer Interface a Tima Addr Register Name Bit Input Capture Tima Counter Prescaler Unbuffered Output Compare Output Compare Buffered Output Compare Pulse-Width Modulation PWM PWM Period and Pulse Width Unbuffered PWM Signal Generation PWM Initialization Buffered PWM Signal Generation 224 Freescale Semiconductor Tima Clock Pin PTE3/TCLKA 16.6 I/O SignalsTima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A 16.7 I/O Registers Toie Tima Overflow Interrupt Enable Bit Trst Tima Reset BitTstop Tima Stop Bit PS20 Tima Clock Source Tima Counter RegistersPS20 Prescaler Select Bits Prescaler Selection Tima Channel Status and Control Registers Tima Counter Modulo Registers CHxIE Channel x Interrupt Enable Bit MSxB Mode Select Bit B MSxA Mode Select Bit aELSxB and ELSxA Edge/Level Select Bits CHxMAX Channel x Maximum Duty Cycle Bit MSxBMSxA ELSxBELSxA Mode ConfigurationMode, Edge, and Level Selection TOVx Toggle-On-Overflow Bit 10. Tima Channel Registers Tima Channel Registers 10. Tima Channel Registers TACH0H/L-TACH3H/L 234 Freescale Semiconductor Timb module is not available in the 56-pin Sdip Chapter Timer Interface B Timb Timer Interface B Timb Block Diagram Highlighting Timb Block and Pins Timb Block Diagram Timb Counter Prescaler Timer Interface B Timb Addr Register Name Bit Freescale Semiconductor 239 240 Freescale Semiconductor Freescale Semiconductor 241 242 Freescale Semiconductor 17.6 I/O Signals Timb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1BTimb Clock Pin PTE0/TCLKB Toie Timb Overflow Interrupt Enable Bit 17.7 I/O RegistersTimb Status and Control Register Trst Timb Reset Bit Tstop Timb Stop BitPS20 Timb Clock Source Timb Counter Modulo Registers Timb Counter Registers Timb Channel Status and Control Registers 248 Freescale Semiconductor PWM 10. Timb Channel Registers TBCH0H/L-TBCH1H/L Timb Channel Registers Flag Protection During Break Interrupts Chapter Development SupportBreak Module BRK Functional Description Development Support Break Module Block Diagram Break Module Registers Low-Power Modes Break Status and Control Register Brka Break Active BitBreak Address Registers Monitor ROM MON Monitor ROM MONBreak Status Register Break Flag Control Register Entering Monitor Mode Mode DifferencesNormal Monitor Mode Monitor Mode Circuit $FFFF Monitor Mode Signal Requirements and Options Data Format Forced Monitor Mode Break Signal CommandsEchoing Command Sequence Read Read Memory CommandWrite Write Memory Command Iread Indexed Read Command Iwrite Indexed Write Command Readsp Read Stack Pointer CommandRUN Run User Program Command Security Baud RateMonitor Baud Rate Selection 13. Monitor Mode Entry Timing Chapter Electrical Specifications Characteristic1 Symbol Value UnitAbsolute Maximum Ratings Functional Operating Range Thermal CharacteristicsElectrical Specifications Characteristic Symbol Value Unit DC Electrical Characteristics DC Electrical CharacteristicsCharacteristic1 Symbol Min Typ2 Max Unit Control Timing Flash Memory CharacteristicsCharacteristic Symbol Min Typ Max Unit Characteristic Symbol Min Max Unit Serial Peripheral Interface Characteristics Serial Peripheral Interface CharacteristicsDiagram Characteristic2 Symbol Min Max Unit Number1 SPI Master Timing SPI Slave Timing CGM Operating Conditions TImer Interface Module CharacteristicsClock Generation Module Component Specifications Characteristic Symbol Min Typ Max CGM Acquisition/Lock Time Specifications CGM Acquisition/Lock Time SpecificationsDescription Symbol Min Typ Max 3FF Analog-to-Digital Converter ADC Characteristics MC Order Number Operating Chapter Ordering Information and Mechanical SpecificationsOrder Numbers Order Numbers 20.3 64-Pin Plastic Quad Flat Pack QFP Ordering Information and Mechanical Specifications Pin Shrink Dual In-Line Package Sdip 20.4 56-Pin Shrink Dual In-Line Package Sdip 278 Freescale Semiconductor Appendix a MC68HC908MR16 MC68HC908MR16 Figure A-1. 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