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Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 12.9.10 Fault Acknowledge Register

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Control Logic Block

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor 153

FFLAG1 — Fault Event Flag 1

The FFLAG1 event bit is set within two CPU cycles after a rising edge on fault pin 1. To clear the

FFLAG1 bit, the user must write a 1 to the FTACK1 bit in the fault acknowledge register.

1 = A fault has occurred on fault pin 1.

0 = No new fault on fault pin 1.

12.9.10 Fault Acknowledge Register

The fault acknowledge register (FTACK) is used to acknowledge and clear the FFLAGs. In addition, it is

used to monitor the current sensing bits to test proper operation.

FTACK4 — Fault Acknowledge 4 Bit

The FTACK4 bit is used to acknowledge and clear FFLAG4. This bit will always read 0. Writing a 1 to

this bit will clear FFLAG4. Writing a 0 will have no effect.

FTACK3 — Fault Acknowledge 3 Bit

The FTACK3 bit is used to acknowledge and clear FFLAG3. This bit will always read 0. Writing a 1 to

this bit will clear FFLAG3. Writing a 0 will have no effect.

FTACK2 — Fault Acknowledge 2 Bit

The FTACK2 bit is used to acknowledge and clear FFLAG2. This bit will always read 0. Writing a 1 to

this bit will clear FFLAG2. Writing a 0 will have no effect.

FTACK1 — Fault Acknowledge 1 Bit

The FTACK1 bit is used to acknowledge and clear FFLAG1. This bit will always read 0. Writing a 1 to

this bit will clear FFLAG1. Writing a 0 will have no effect.

DT6 — Dead-Time 6 Bit

Current sensing pin IS3 is monitored immediately before dead-time ends due to the assertion of

PWM6.

DT5 — Dead-Time 5 Bit

Current sensing pin IS3 is monitored immediately before dead-time ends due to the assertion of

PWM5.

DT4 — Dead-Time 4 Bit

Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of

PWM4.

DT3 — Dead-Time 3 Bit

Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of

PWM3.

Address: $0024

Bit 7654321Bit 0

Read: 0 0 DT6 DT5 DT4 DT3 DT2 DT1

Write: FTACK4 FTACK3 FTACK2 FTACK1

Reset:00000000

= Unimplemented

Figure 12-45. Fault Acknowledge Register (FTACK)

Contents

Main Page Page Revision History List of Chapters Page Table of Contents Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC) Chapter 4 Clock Generator Module (CGM) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Low-Voltage Inhibit (LVI) Chapter 10 Input/Output (I/O) Ports (PORTS) Chapter 11 Power-On Reset (POR) Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) Chapter 13 Serial Communications Interface Module (SCI) Chapter 14 System Integration Module (SIM) Chapter 15 Serial Peripheral Interface Module (SPI) Chapter 16 Timer Interface A (TIMA) Chapter 17 Timer Interface B (TIMB) Chapter 18 Development Support Chapter 19 Electrical Specifications Chapter 20 Ordering Information and Mechanical Specifications Appendix A MC68HC908MR16 Chapter 1 General Description 1.1 Introduction 1.2 Features 1.3 MCU Block Diagram Freescale Semiconductor 19 MCU Block Diagram Figure 1-1. MCU Block Diagram General Description 20 Freescale Semiconductor 1.4 Pin Assignments Figure 1-2. 64-Pin QFP Pin Assignments Pin Assignments Figure 1-3. 56-Pin SDIP Pin Assignments Freescale Semiconductor 21 Note: PTC1, PTE0, PTE1, PTE2, PTF0, PTF1, PTF2, and PTF3 are removed from this package. 1.4.1 Power Supply Pins (VDD and VSS) 1.4.2 Oscillator Pins (OSC1 and OSC2) 1.4.3 External Reset Pin (RST) 1.4.4 External Interrupt Pin (IRQ) 1.4.5 CGM Power Supply Pins (VDDA and VSSAD) Page Page Chapter 2 Memory 2.1 Introduction 2.2 Unimplemented Memory Locations 2.3 Reserved Memory Locations 2.4 I/O Section 2.5 Memory Map Figure 2-1. MC68HC908MR32 Memory Map Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 2 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 4 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 8) Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8) Table 2-1 is a list of vector locations. Table 2-1. Vector Addresses Priority 2.6 Monitor ROM 2.7 Random-Access Memory (RAM) 2.8 FLASH Memory (FLASH) 2.8.1 FLASH Control Register 2.8.2 FLASH Page Erase Operation 2.8.3 FLASH Mass Erase Operation 2.8.4 FLASH Program Operation Figure 2-4. FLASH Programming Flowchart ALGORITHM FOR PROGRAMMING A ROW (64 BYTES) OF FLASH MEMORY 2.8.5 FLASH Block Protection 2.8.6 FLASH Block Protect Register 2.8.7 Wait Mode 2.8.8 Stop Mode Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction 3.2 Features 3.3 Functional Description 46 Freescale Semiconductor Figure 3-1. Block Diagram Highlighting ADC Block and Pins 3.3.1 ADC Port I/O Pins 3.3.2 Voltage Conversion 3.3.3 Conversion Time 3.3.4 Continuous Conversion 3.3.5 Result Justification 3.3.6 Monotonicity 3.4 Interrupts 3.5 Wait Mode 3.6 I/O Signals 3.6.1 ADC Analog Power Pin (VDDAD) 3.6.2 ADC Analog Ground Pin (VSSAD) 3.7 I/O Registers 3.7.1 ADC Status and Control Register Table 3-1. Mux Channel Select 3.7.2 ADC Data Register High 3.7.3 ADC Data Register Low 3.7.4 ADC Clock Register Page Chapter 4 Clock Generator Module (CGM) 4.1 Introduction 4.2 Features 4.3 Functional Description Figure 4-1. CGM Block Diagram Figure 4-2. CGM I/O Register Summary 4.3.1 Crystal Oscillator Circuit 4.3.2 Phase-Locked Loop Circuit (PLL) Page Page 4.3.3 Base Clock Selector Circuit 4.3.4 CGM External Connections 4.4 I/O Signals 4.4.1 Crystal Amplifier Input Pin (OSC1) 4.4.2 Crystal Amplifier Output Pin (OSC2) 4.4.3 External Filter Capacitor Pin (CGMXFC) 4.4.4 PLL Analog Power Pin (VDDA) 4.5 CGM Registers 4.5.1 PLL Control Register 4.5.2 PLL Bandwidth Control Register 4.5.3 PLL Programming Register 4.6 Interrupts 4.7 Wait Mode 4.8 Acquisition/Lock Time Specifications 4.8.1 Acquisition/Lock Time Definitions 4.8.2 Parametric Influences on Reaction Time 4.8.3 Choosing a Filter Capacitor 4.8.4 Reaction Time Calculation Page Chapter 5 Configuration Register (CONFIG) 5.1 Introduction 5.2 Functional Description 5.3 Configuration Register Chapter 6 Computer Operating Properly (COP) 6.1 Introduction 6.2 Functional Description 6.3 I/O Signals 6.3.1 CGMXCLK 6.3.2 COPCTL Write 6.3.3 Power-On Reset 6.3.4 Internal Reset Page Page Chapter 7 Central Processor Unit (CPU) 7.1 Introduction 7.2 Features 7.3 CPU Registers 7.3.1 Accumulator 7.3.2 Index Register 7.3.3 Stack Pointer 7.3.4 Program Counter 7.3.5 Condition Code Register 7.4 Arithmetic/Logic Unit (ALU) 7.5 Low-Power Modes 7.5.1 Wait Mode 7.5.2 Stop Mode 7.6 CPU During Break Interrupts 7.7 Instruction Set Summary Instruction Set Summary Freescale Semiconductor 85 Table 7-1. Instruction Set Summary (Sheet 2 of 6) Table 7-1. Instruction Set Summary (Sheet 3 of 6) Instruction Set Summary Freescale Semiconductor 87 Table 7-1. Instruction Set Summary (Sheet 4 of 6) Table 7-1. Instruction Set Summary (Sheet 5 of 6) Opcode Map Freescale Semiconductor 89 7.8 Opcode Map See Table 7-2. Table 7-1. Instruction Set Summary (Sheet 6 of 6) MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev. 6.1 90 Freescale Semiconductor Table 7-2. Opcode Map * Chapter 8 External Interrupt (IRQ) 8.1 Introduction Figure 8-2. IRQ I/O Register Summary 8.2 Features Features of the IRQ module include: A dedicated external interrupt pin, IRQ Hysteresis buffers 8.4 IRQ Pin IRQ Pin Figure 8-3. IRQ Interrupt Flowchart Freescale Semiconductor 93 8.5 IRQ Status and Control Register Page Page Chapter 9 Low-Voltage Inhibit (LVI) 9.1 Introduction 9.2 Features 9.3 Functional Description 9.3.1 Polled LVI Operation 9.3.2 Forced Reset Operation 9.3.3 False Reset Protection 9.3.4 LVI Trip Selection 9.4 LVI Status and Control Register 9.5 LVI Interrupts 9.6 Wait Mode Page Chapter 10 Input/Output (I/O) Ports (PORTS) 10.1 Introduction Figure 10-1. I/O Port Register Summary (Continued) 10.2 Port A 10.2.1 Port A Data Register 10.2.2 Data Direction Register A 10.3 Port B 10.3.1 Port B Data Register 10.3.2 Data Direction Register B 10.4 Port C 10.4.1 Port C Data Register 10.4.2 Data Direction Register C 10.5 Port D 10.6 Port E 10.6.1 Port E Data Register 10.6.2 Data Direction Register E 10.7 Port F 10.7.1 Port F Data Register 10.7.2 Data Direction Register F Page Page Chapter 11 Power-On Reset (POR) 11.1 Introduction 11.2 Functional Description Page Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) 12.1 Introduction 12.2 Features Figure 12-1. Block Diagram Highlighting PWMMC Block and Pins Figure 12-2. PWM Module Block Diagram Figure 12-3. Register Summary (Sheet 1 of 3) Figure 12-3. Register Summary (Sheet 2 of 3) Figure 12-3. Register Summary (Sheet 3 of 3) 12.3 Timebase 12.3.1 Resolution Page 12.3.2 Prescaler 12.4 PWM Generators 12.4.1 Load Operation Page Figure 12-8. Center-Aligned PWM Value Loading Figure 12-9. Center-Aligned Loading of Modulus Figure 12-10. Edge-Aligned PWM Value Loading 12.4.2 PWM Data Overflow and Underflow Conditions 12.5 Output Control 12.5.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs 12.5.2 Dead-Time Insertion Figure 12-14. Dead-Time Generators Output Control Freescale Semiconductor 129 Figure 12-15. Effects of Dead-Time Insertion Figure 12-16. Dead-Time at Duty Cycle Boundaries 12.5.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing I+ I- Page 12.5.4 Output Polarity Figure 12-21. PWM Polarity 12.5.5 PWM Output Port Control Figure 12-23. Dead-Time Insertion During OUTCTL = 1 Figure 12-24. Dead-Time Insertion During OUTCTL = 1 12.6 Fault Protection 12.6.1 Fault Condition Input Pins Figure 12-26. PWM Disabling Scheme 138 Freescale Semiconductor Page Page 12.6.2 Software Output Disable 12.6.3 Output Port Control 12.7 Initialization and the PWMEN Bit 12.8 PWM Operation in Wait Mode 12.9 Control Logic Block 12.9.1 PWM Counter Registers 12.9.2 PWM Counter Modulo Registers 12.9.3 PWMx Value Registers 12.9.4 PWM Control Register 1 Page 12.9.5 PWM Control Register 2 Page 12.9.6 Dead-Time Write-Once Register 12.9.7 PWM Disable Mapping Write-Once Register 12.9.8 Fault Control Register Page 12.9.9 Fault Status Register 12.9.10 Fault Acknowledge Register 12.9.11 PWM Output Control Register 12.10 PWM Glossary Page Chapter 13 Serial Communications Interface Module (SCI) 13.1 Introduction 13.2 Features 158 Freescale Semiconductor Serial Communications Interface Module (SCI) Figure 13-1. Block Diagram Highlighting SCI Block and Pins 13.3 Functional Description Figure 13-2. SCI Module Block Diagram 13.3.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 13-4. Figure 13-4. SCI Data Formats R Figure 13-3. SCI I/O Register Summary 13.3.2 Transmitter Figure 13-5 shows the structure of the SCI transmitter. Figure 13-5. SCI Transmitter Page 13.3.3 Receiver Serial Communications Interface Module (SCI) 164 Freescale Semiconductor Page Page Page 13.4 Wait Mode 13.5 SCI During Break Module Interrupts 13.6 I/O Signals 13.6.1 PTF5/TxD (Transmit Data) 13.6.2 PTF4/RxD (Receive Data) 13.7 I/O Registers 13.7.1 SCI Control Register 1 Page 13.7.2 SCI Control Register 2 Page 13.7.3 SCI Control Register 3 13.7.4 SCI Status Register 1 Page 13.7.5 SCI Status Register 2 13.7.6 SCI Data Register 13.7.7 SCI Baud Rate Register Page Table 13-7. SCI Baud Rate Selection Examples Page Chapter 14 System Integration Module (SIM) 14.1 Introduction 14.2 SIM Bus Clock Control and Generation 14.2.1 Bus Timing 14.2.2 Clock Startup from POR or LVI Reset 14.2.3 Clocks in Wait Mode 14.3 Reset and System Initialization 14.3.1 External Pin Reset 14.3.2 Active Resets from Internal Sources Page 14.4 SIM Counter 14.4.1 SIM Counter During Power-On Reset 14.4.2 SIM Counter and Reset States 14.5 Exception Control 14.5.1 Interrupts System Integration Module (SIM) Figure 14-8. Interrupt Processing 188 Freescale Semiconductor Page 14.5.2 Reset 14.6 Low-Power Mode 14.6.1 Wait Mode 14.6.2 Stop Mode 14.7 SIM Registers 14.7.1 SIM Break Status Register 14.7.2 SIM Reset Status Register 14.7.3 SIM Break Flag Control Register Page Chapter 15 Serial Peripheral Interface Module (SPI) 15.1 Introduction 15.2 Features 15.3 Pin Name Conventions 196 Freescale Semiconductor Figure 15-1. Block Diagram Highlighting SPI Block and Pins 15.4 Functional Description Figure 15-2. SPI Module Block Diagram 15.4.1 Master Mode 15.4.2 Slave Mode 15.5 Transmission Formats 15.5.1 Clock Phase and Polarity Controls 15.5.2 Transmission Format When CPHA = 0 15.5.3 Transmission Format When CPHA = 1 15.5.4 Transmission Initiation Latency Page 15.6 Error Conditions 15.6.1 Overflow Error 15.6.2 Mode Fault Error Page 15.7 Interrupts 15.8 Resetting the SPI 15.9 Queuing Transmission Data Serial Peripheral Interface Module (SPI) 208 Freescale Semiconductor Figure 15-12. SPRF/SPTE CPU Interrupt Timing 15.10 Low-Power Mode 15.11 I/O Signals 15.11.1 MISO (Master In/Slave Out) 15.11.2 MOSI (Master Out/Slave In) 15.11.3 SPSCK (Serial Clock) 15.11.4 SS (Slave Select) 15.11.5 VSS (Clock Ground) 15.12 I/O Registers 15.12.1 SPI Control Register Page 15.12.2 SPI Status and Control Register Page 15.12.3 SPI Data Register Chapter 16 Timer Interface A (TIMA) 16.1 Introduction 16.2 Features 216 Freescale Semiconductor Timer Interface A (TIMA) Figure 16-1. Block Diagram Highlighting TIMA Block and Pins Features Freescale Semiconductor 217 Figure 16-2. TIMA Block Diagram Figure 16-3. TIM I/O Register Summary 16.3 Functional Description 16.3.1 TIMA Counter Prescaler 16.3.2 Input Capture 16.3.3 Output Compare 16.3.4 Pulse-Width Modulation (PWM) Page Page 16.4 Interrupts 16.5 Wait Mode 16.6 I/O Signals 16.6.1 TIMA Clock Pin (PTE3/TCLKA) 16.6.2 TIMA Channel I/O Pins (PTE4/TCH0APTE7/TCH3A) 16.7 I/O Registers 16.7.1 TIMA Status and Control Register Page 16.7.2 TIMA Counter Registers 16.7.3 TIMA Counter Modulo Registers 16.7.4 TIMA Channel Status and Control Registers Page Page Page 16.7.5 TIMA Channel Registers Figure 16-10. TIMA Channel Registers (TACH0H/LTACH3H/L) (Continued) Page Chapter 17 Timer Interface B (TIMB) 17.1 Introduction 17.2 Features 17.3 Functional Description 236 Freescale Semiconductor Figure 17-1. Block Diagram Highlighting TIMB Block and Pins Figure 17-2. TIMB Block Diagram Figure 17-3. TIMB I/O Register Summary 17.3.1 TIMB Counter Prescaler 17.3.2 Input Capture 17.3.3 Output Compare 17.3.4 Pulse-Width Modulation (PWM) Page Page 17.4 Interrupts 17.5 Wait Mode 17.6 I/O Signals 17.6.1 TIMB Clock Pin (PTE0/TCLKB) 17.6.2 TIMB Channel I/O Pins (PTE1/TCH0BPTE2/TCH1B) 17.7 I/O Registers 17.7.1 TIMB Status and Control Register Page 17.7.2 TIMB Counter Registers 17.7.3 TIMB Counter Modulo Registers 17.7.4 TIMB Channel Status and Control Registers Page Page 17.7.5 TIMB Channel Registers Chapter 18 Development Support 18.1 Introduction 18.2 Break Module (BRK) 18.2.1 Functional Description Figure 18-1. Break Module Block Diagram Figure 18-2. I/O Register Summary 18.2.2 Low-Power Modes 18.2.3 Break Module Registers Page 18.3 Monitor ROM (MON) 18.3.1 Functional Description Monitor ROM (MON) Freescale Semiconductor 257 Figure 18-8. Monitor Mode Circuit S2 Position A Bus clock = CGMXCLK 4 or CGMVCLK 4 S2 Position B Bus clock = CGMXCLK 2 S3 Position A Parallel communication S3 Position B Serial communication 258 Freescale Semiconductor Development Support Table 18-2. Monitor Mode Signal Requirements and Options Page Page Table 18-3. READ (Read Memory) Command Table 18-4. WRITE (Write Memory) Command Table 18-5. IREAD (Indexed Read) Command Table 18-6. IWRITE (Indexed Write) Command Table 18-7. READSP (Read Stack Pointer) Command Table 18-8. RUN (Run User Program) Command 18.3.2 Security Development Support Figure 18-13. Monitor Mode Entry Timing 264 Freescale Semiconductor Chapter 19 Electrical Specifications 19.1 Introduction 19.2 Absolute Maximum Ratings 19.3 Functional Operating Range 19.4 Thermal Characteristics 19.5 DC Electrical Characteristics 19.6 FLASH Memory Characteristics 19.7 Control Timing 19.8 Serial Peripheral Interface Characteristics Electrical Specifications Figure 19-1. SPI Master Timing 270 Freescale Semiconductor a) SPI Master Timing (CPHA = 0) b) SPI Master Timing (CPHA = 1) Serial Peripheral Interface Characteristics Figure 19-2. SPI Slave Timing Freescale Semiconductor 271 a) SPI Slave Timing (CPHA = 0) b) SPI Slave Timing (CPHA = 1) 19.9 TImer Interface Module Characteristics 19.10 Clock Generation Module Component Specifications 19.11 CGM Operating Conditions 19.12 CGM Acquisition/Lock Time Specifications 19.13 Analog-to-Digital Converter (ADC) Characteristics Chapter 20 Ordering Information and Mechanical Specifications 20.1 Introduction 20.2 Order Numbers Page Page Page Page $FF00 Figure A-1. MC68HC908MR16 Memory Map $FF7F Page How to Reach Us: