I/O Registers

17.7.4 TIMB Channel Status and Control Registers

Each of the TIMB channel status and control registers:

Flags input captures and output compares

Enables input capture and output compare interrupts

Selects input capture, output compare, or PWM operation

Selects high, low, or toggling output on output compare

Selects rising edge, falling edge, or any edge as the active input capture trigger

Selects output toggling on TIMB overflow

Selects 0 percent and 100 percent PWM duty cycle

Selects buffered or unbuffered output compare/PWM operation

Register Name and Address:

TBSC0 — $0056

 

 

 

 

 

Bit 7

6

5

4

3

2

1

Bit 0

 

 

 

 

 

 

 

 

 

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

 

 

Write:

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset:

0

0

0

0

0

0

0

0

Register Name and Address:

TBSC1 — $0059

 

 

 

 

 

Bit 7

6

5

4

3

2

1

Bit 0

 

 

 

 

 

 

 

 

 

Read:

CH1F

CH1IE

0

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

 

 

 

Write:

0

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset:

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

R

= Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 17-8. TIMB Channel Status and Control Registers (TBSC0–TBSC1)

CHxF — Channel x Flag

When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMB counter registers matches the value in the TIMB channel x registers.

When CHxIE = 1, clear CHxF by reading TIMB channel x status and control register with CHxF set, and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.

Reset clears the CHxF bit. Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x

0 = No input capture or output compare on channel x

CHxIE — Channel x Interrupt Enable Bit

This read/write bit enables TIMB CPU interrupts on channel x. Reset clears the CHxIE bit.

1 = Channel x CPU interrupt requests enabled

0 = Channel x CPU interrupt requests disabled

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

247

Page 247
Image 247
Freescale Semiconductor MC68HC908MR16 Timb Channel Status and Control Registers, CHxIE Channel x Interrupt Enable Bit

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

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The MC68HC908MR32 variant is equipped with 32KB of flash memory, which allows for the storage of complex programs and extensive data handling. In contrast, the MC68HC908MR16 features 16KB of flash memory, making it ideal for simpler applications. Both microcontrollers also come with 1KB of RAM, enabling efficient data processing and real-time operations.

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