CY7C67300
Sequence Select (Bit 6)
The Sequence Select bit determines whether a DATA0 or a DATA1 is sent for the next data toggle. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.
1:Send a DATA1
0:Send a DATA0
Stall Enable (Bit 5)
The Stall Enable bit sends a Stall in response to the next request (unless it is a setup request, which are always ACKed). This is a sticky bit and continues to respond with Stalls until cleared by firmware.
1:Send Stall
0:Do not send Stall
ISO Enable (Bit 4)
The ISO Enable bit enables and disables an isochronous trans- action. This bit is only valid for EPs
1:Enable isochronous transaction
0:Disable isochronous transaction
NAK Interrupt Enable (Bit 3)
The NAK Interrupt Enable bit enables and disables the gener- ation of an Endpoint n interrupt when the device responds to the host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable register must also be set. When a NAK is sent to the host, the corresponding EP Interrupt Flag in the Device n Status register is set. In addition, the NAK Flag in the Device n Endpoint n Status register is set.
1:Enable NAK interrupt
0:Disable NAK interrupt
Device n Endpoint n Address Register [R/W]
Direction Select (Bit 2)
The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If the data stage direction is different from what is set in this bit, it gets NAKed and either the IN Exception Flag or the OUT Exception Flag is set in the Device n Endpoint n Status register. If a setup packet is received and the Direction Select bit is set incorrectly, the setup is ACKed and the Setup Status Flag is set (refer to the setup bit of the Device n Endpoint n Status Register [R/W] on page 41 for details).
1:OUT transfer (host to device)
0:IN transfer (device to host)
Enable (Bit 1)
Set the Enable bit to allow transfers to the endpoint. If Enable is set to ‘0’ then all USB traffic to this endpoint is ignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs are automat- ically returned from this endpoint (except setup packets which are always ACKed as long as the Enable bit is set).
1:Enable transfers to an endpoint
0:Do not allow transfers to an endpoint
Arm Enable (Bit 0)
The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete.
1:Arm endpoint
0:Endpoint disarmed
Reserved
Write all reserved bits with ’0’.
■Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]
■Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]
■Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]
■Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]
■Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]
■Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]
■Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]
■Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]
Table 64. Device n Endpoint n Address Register
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field |
|
|
|
| Address... |
|
|
| |
Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | X | X | X | X |
| X | X | X | X |
Bit # | 7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Field |
|
|
|
| ...Address |
|
|
| |
Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | X | X | X | X |
| X | X | X | X |
Document #: | Page 39 of 99 |
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