CY7C67300
Register Description
The Device n Status register provides status information for device operation. Pending interrupts can be cleared by writing a ‘1’ to the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Device 1 and is a reserved bit in Device 2.
1:Interrupt triggered
0:Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Device 1 and is a reserved bit in Device 2.
1:Interrupt triggered
0:Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt triggered.
1:Interrupt triggered
0:Interrupt did not trigger
Reset Interrupt Flag (Bit 8)
The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt triggered.
1:Interrupt triggered
0:Interrupt did not trigger
EP7 Interrupt Flag (Bit 7)
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1:Interrupt triggered
0:Interrupt did not trigger
EP6 Interrupt Flag (Bit 6)
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1:Interrupt triggered
0:Interrupt did not trigger
EP5 Interrupt Flag (Bit 5)
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1:Interrupt triggered
0:Interrupt did not trigger
EP4 Interrupt Flag (Bit 4)
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1:Interrupt triggered
0:Interrupt did not trigger
EP3 Interrupt Flag (Bit 3)
The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1:Interrupt triggered
0:Interrupt did not trigger
Document #: | Page 46 of 99 |
[+] Feedback
