SPI Data Register 0xC0D6 R/W | Cypress CY7C67300 instruction

CY7C67300

SPI Data Register [0xC0D6] [R/W]

Table 114. SPI Data Register

Bit #

15

14

13

12

11

10

9

8

Field

Reserved

Read/Write

-

-

-

-

-

-

-

-

Default

X

X

X

X

X

X

X

X

Bit #

7

6

5

4

3

2

1

0

Field

Data

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

X

X

X

X

X

X

X

X

Register Description

The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte mode. This receive data is valid when the Receive Interrupt Bit of the SPI Status register is set to ‘1’ (RxIntVal triggers) or the Receive Data Ready bit of the SPI Control register is set to ‘1’. Writing to this register in PIO byte mode initiates a transfer of data, the number of bits defined by Transmit Bit Length field in the SPI Control register.

SPI Transmit Address Register [0xC0D8] [R/W]

Table 115. SPI Transmit Address Register

Data (Bits [7:0])

The Data field contains data received or to be transmitted on the SPI port.

Reserved

Write all reserved bits with ’0’.

Bit #	15	14	13	12		11	10	9	8
Field					Address...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field					...Address
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Register Description

The SPI Transmit Address register is used as the base address for the SPI transmit DMA.

Address (Bits [15:0])

The Address field sets the base address for the SPI transmit DMA.

Document #: 38-08015 Rev. *J

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Cypress CY7C67300 manual SPI Data Register 0xC0D6 R/W, SPI Transmit Address Register 0xC0D8 R/W

Contents

Typical Applications EZ-Host FeaturesCY7C67300 Block Diagram Interface Descriptions IntroductionFunctional Overview USB Interface Interface Options for External Memory Bus Pins MEM Pins OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number External Memory Interface Up to 256k x 16 External Code/Data Page Mode External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number External Memory Interface Block Diagrams Serial Peripheral Interface General Purpose IO Interface GpioUart Interface I2C Eeprom Interface Programmable Pulse/PWM Interface High-Speed Serial Interface IDE Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 Host Port Interface Actual IDE Throughput ModeIDE Interface Pins Pin Name Pin Number Charge Pump Interface Pins Pin Name Pin Number Booster Interface Booster PinsCrystal Pins Crystal Pins Pin Name Pin Number Operational Modes Boot Configuration InterfaceBoot Configuration Interface Boot Mode Sleep Power Savings and Reset DescriptionPower Saving Mode Description Memory Map Document # 38-08015 Rev. *JPage 15 Bank Selected 0xC018 0xC01A Processor Control Registers Registers Revision Register Bank RegisterBank Register Example Hex Value Binary Value Reserved CPU Speed Definition Processor Speed Host/Device 1B Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 2A Wake Enable Bit SPI Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit OTG Interrupt Enable Bit Uart Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Out Mailbox Interrupt Enable Bit Port 1B Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 2A Diagnostic Enable Bit External Memory Registers Extended Page n Map Register Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map Register R/W Timer Registers WDT Enable Bit Watchdog Timer RegisterTimeout Flag Bit Lock Enable Bit Port B D+ Status Bit Timer n RegisterGeneral USB Registers USB n Control Register Enable Mode Select BitPort B Resistors Enable Bit Port a Resistors Enable Bit USB Host Only Register Register Name Address Host 1/Host Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only Registers Sequence Select Bit Sync Enable BitHost n Address Register ISO Enable Bit Arm Enable Bit NAK Flag Bit Port Select BitUnderflow Flag Bit Stall Flag Bit Host n PID Register Error Flag BitSequence Status Bit Host n PID Register W Host n Count Result Register Endpoint Select Bits PID Select DefinitionPID Select Host n Count Result Register R Host n Device Address Register Host n Interrupt Enable RegisterVbus Interrupt Enable Bit ID Interrupt Enable Bit Port B Connect Change Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port a Wake Interrupt Enable Bit Port B Connect Change Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port a Wake Interrupt Flag Bit Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6 Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host n Frame Register R Device n Endpoint n Control Register IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control Register R/W Direction Select Bit Stall Enable BitNAK Interrupt Enable Bit Enable Bit Device n Endpoint n Count Register Device n Endpoint n Count Register R/W Exception Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register OUT Exception Flag Bit Device n Endpoint n Count Result Register Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result Register R/W Device n Port Select Register Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select Register R/W EP6 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable Bit Device n Status Register R/W EP0 Interrupt Enable BitDevice n Address Register W Device n Address Register EP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag Bit EP1 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP2 Interrupt Flag Bit OTG Control Register Reserved Vbus Pull-up Enable BitOTG Control Registers Device n SOF/EOP Count Register Gpio Registers HSS Enable Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 Gpio n Input Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Output Data Register IDE Registers IDE Start Address Register Mode Select DefinitionIDE Start Address Register 0xC04A R/W IDE Control Register IDE Interrupt Enable BitIDE Enable Bit IDE Stop Address Register HSS Registers Register Name Address HSS RegistersIDE PIO Port Registers 0xC050 0xC06F R/W HSS Control Register Xoff Enable BitCTS Enable Bit Receive Interrupt Enable Bit HSS Baud Rate Register Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag Bit HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register Transmit Gap Select Bits HSS Receive Counter Register HSS Receive Counter Register 0xC07A R/W HSS Transmit Counter Register HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter Register 0xC07E R/W Interrupt Routing Register Vbus to HPI Enable BitHPI Registers HPI Breakpoint Register HPI Registers Register Name Address SOF/EOP1 to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP2 to CPU Enable Bit HPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register SIEXmsg Register ID Flag Bit Reset2 Flag BitHPI Status Port Vbus Flag Bit Mailbox Out Flag Bit Reset1 Flag BitSPI Registers Done1 Flag Bit Master Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable Bit SCK Strobe Bit Byte Mode BitRead Enable Bit SPI Control Register Fifo Error Flag Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Transfer Interrupt Enable Bit Transfer Interrupt Flag Bit Receive Interrupt Flag BitTransmit Interrupt Flag Bit SPI Interrupt Clear Register SPI CRC Value Register Receive CRC Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit CRC Clear Bit SPI Transmit Address Register SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address Register 0xC0D8 R/W SPI Receive Count Register SPI Transmit Count RegisterSPI Receive Address Register Uart Registers Uart Data Register 0xC0E4 R/W Uart Status Register 0xC0E2 RUart Status Register Receive buffer full Receive buffer empty PWM Control Register PWM Enable BitPWM Registers PWM Registers Register Name Address PWM 0 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 1 Enable Bit PWM n Stop Register PWM n Start Register R/WPWM n Start Register PWM n Stop Register R/W PWM Cycle Count Register PWM Cycle Count Register 0xC0FA R/W Pin Descriptions Name Type Pin DiagramPin Descriptions D8/MISO D11/MOSIMosi SPI Mosi SCK SPI SCK GPIO26/CTS/PWM3 GPIO29/OTGIDGPIO28/TX GPIO27/RX Tie to Gnd for normal operation Booster Power input 2.7V to Crystal Requirements XTALIN, Xtalout DC CharacteristicsAbsolute Maximum Ratings Operating Conditions GND USB Transceiver Clock Timing AC Timing CharacteristicsReset Timing LOW Sram Read Cycle15Sram Read Cycle Parameters Description Min Typical Max Unit High Sram Write CycleSram Write Cycle Parameters Parameter Description Min Typical Max Unit SDA OUT I2C Eeprom Timing-Serial IOSCL HPI Host Port Interface Write Cycle Timing Read Cycle Time Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse Width IDE Timing HSS Byte Mode TransmitHSS Block Mode Transmit HSS Byte and Block Mode Receive Register Summary Register SummaryHardware CTS/RTS Handshake HSS SOF/EOP CRC SOF/EOP2 Pb-Free Package DiagramsOrdering Information Ordering Information Ordering Code Package Type Orig. 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