Sequence Select Bit, Sync Enable Bit | Cypress CY7C67300 manual

CY7C67300

Sequence Select (Bit 6)

The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.

1:Send DATA1

0:Send DATA0

Sync Enable (Bit 5)

The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.

1:The next enabled packet is transferred after the SOF or EOP packet is transmitted

0:The next enabled packet is transferred as soon as the SIE is free

Host n Address Register [R/W]

■Host 1 Address Register 0xC082

■Host 2 Address Register 0xC0A2

Table 49. Host n Address Register

ISO Enable (Bit 4)

The ISO Enable bit enables or disables an isochronous trans- action.

1:Enable isochronous transaction

0:Disable isochronous transaction

Arm Enable (Bit 0)

The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction is complete.

1:Arm endpoint and begin transaction

0:Endpoint disarmed

Reserved

Write all reserved bits with ’0’.

Bit #	15	14	13	12		11	10	9	8
Field					Address...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field					...Address
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Register Description

The Host n Address register is used as the base pointer into memory space for the current host transactions.

Host n Count Register [R/W]

■Host 1 Count Register 0xC084.

■Host 2 Count Register 0xC0A4.

Table 50. Host n Count Register

Address (Bits [15:0])

The Address field sets the address pointer into internal RAM or ROM.

Bit #	15	14	13	12		11	10	9		8
Field	Reserved	Port			Reserved				Count...
Field		Select
Read/Write	-	R/W	-	-		-	-	R/W		R/W
Default	0	0	0	0		0	0	0		0

Bit #	7	6	5	4		3	2	1	0
Field					...Count
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	0

Document #: 38-08015 Rev. *J

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Cypress CY7C67300 manual Sequence Select Bit, Sync Enable Bit, Host n Address Register ISO Enable Bit, Arm Enable Bit

Contents

EZ-Host Features CY7C67300 Block DiagramTypical Applications Introduction Functional OverviewInterface Descriptions Interface Options for External Memory Bus Pins MEM Pins USB Interface USB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberOTG Interface External Memory Interface External Memory Interface Block Diagrams External Memory Interface PinsExternal Memory Interface Pins Pin Name Pin Number Up to 256k x 16 External Code/Data Page Mode I2C Eeprom Interface General Purpose IO Interface GpioUart Interface Serial Peripheral Interface High-Speed Serial Interface Programmable Pulse/PWM Interface Host Port Interface HPI Interface Pins 3 Pin Name Pin NumberHPI Interface Pins 3 IDE Interface Charge Pump Interface Pins Pin Name Pin Number IDE Throughput ModeIDE Interface Pins Pin Name Pin Number Actual Crystal Pins Pin Name Pin Number Booster PinsCrystal Pins Booster Interface Boot Mode Boot Configuration InterfaceBoot Configuration Interface Operational Modes Power Savings and Reset Description Power Saving Mode DescriptionSleep Memory Map Bank Selected 0xC018 0xC01A Document # 38-08015 Rev. *JPage 15 Registers Processor Control Registers Reserved Bank RegisterBank Register Example Hex Value Binary Value Revision Register CPU Speed Definition Processor Speed Host/Device 2A Wake Enable Bit Power Control RegisterHost/Device 2B Wake Enable Bit Host/Device 1B Wake Enable Bit OTG Interrupt Enable Bit Sleep Enable BitInterrupt Enable Register Halt Enable Bit SPI Interrupt Enable Bit Out Mailbox Interrupt Enable Bit HSS Interrupt Enable BitMailbox Interrupt Enable Bit Uart Interrupt Enable Bit Port 2A Diagnostic Enable Bit USB Diagnostic RegisterPort 2B Diagnostic Enable Bit Port 1B Diagnostic Enable Bit External Memory Registers Extended Page n Map Register R/W Upper Address Enable Register 0xC038 R/WUpper Address Enable Bit Extended Page n Map Register Timer Registers Lock Enable Bit Watchdog Timer RegisterTimeout Flag Bit WDT Enable Bit USB n Control Register Timer n RegisterGeneral USB Registers Port B D+ Status Bit Port a Resistors Enable Bit Mode Select BitPort B Resistors Enable Bit Enable USB Host Only Registers Port a SOF/EOP Enable Bit ReservedPreamble Enable Bit USB Host Only Register Register Name Address Host 1/Host Arm Enable Bit Sync Enable BitHost n Address Register ISO Enable Bit Sequence Select Bit Stall Flag Bit Port Select BitUnderflow Flag Bit NAK Flag Bit Host n PID Register W Error Flag BitSequence Status Bit Host n PID Register Host n Count Result Register R PID Select DefinitionPID Select Host n Count Result Register Endpoint Select Bits ID Interrupt Enable Bit Host n Interrupt Enable RegisterVbus Interrupt Enable Bit Host n Device Address Register Port a Wake Interrupt Enable Bit SOF/EOP Interrupt Enable BitPort B Wake Interrupt Enable Bit Port B Connect Change Interrupt Enable Bit Port a Wake Interrupt Flag Bit SOF/EOP Interrupt Flag BitPort B Wake Interrupt Flag Bit Port B Connect Change Interrupt Flag Bit Host n Frame Register R Host n SOF/EOP Counter Register RHost n SOF/EOP Counter Register Host 1 Frame Register 0xC096 Host 2 Frame Register 0xC0B6 Device n Endpoint n Control Register R/W IN/OUT Ignore Enable BitUSB Device Only Registers Device n Endpoint n Control Register Enable Bit Stall Enable BitNAK Interrupt Enable Bit Direction Select Bit Device n Endpoint n Count Register R/W Device n Endpoint n Count Register OUT Exception Flag Bit Device n Endpoint n Status Register R/WDevice n Endpoint n Status Register Exception Flag Bit Device n Endpoint n Count Result Register R/W Setup Flag BitSequence Flag Bit Device n Endpoint n Count Result Register Device n Port Select Register R/W Device n Interrupt Enable Register R/WDevice n Interrupt Enable Register Port Select Bit Device n Port Select Register EP7 Interrupt Enable Bit SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP6 Interrupt Enable Bit Device n Address Register EP0 Interrupt Enable BitDevice n Address Register W Device n Status Register R/W EP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag Bit EP2 Interrupt Flag Bit SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits EP1 Interrupt Flag Bit Device n SOF/EOP Count Register Vbus Pull-up Enable BitOTG Control Registers OTG Control Register Reserved Gpio Registers Mode Select Definition Gpio Configuration 108 Write Protect Enable BitSAS Enable Bit HSS Enable Bit Gpio n Output Data Register Interrupt 0 Enable BitInterrupt 0 Polarity Select Bit Reserved Gpio n Input Data Register IDE Registers Mode Select Definition IDE Start Address Register 0xC04A R/WIDE Start Address Register IDE Stop Address Register IDE Interrupt Enable BitIDE Enable Bit IDE Control Register HSS Registers IDE PIO Port Registers 0xC050 0xC06F R/WHSS Registers Register Name Address Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit HSS Control Register Receive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit HSS Baud Rate Register Transmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Transmit Gap Register HSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Counter Register HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHSS Transmit Address Register HSS Transmit Counter Register HPI Breakpoint Register HPI Registers Register Name Address Vbus to HPI Enable BitHPI Registers Interrupt Routing Register SOF/EOP2 to CPU Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit SOF/EOP1 to HPI Enable Bit SIEXmsg Register SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/W Vbus Flag Bit Reset2 Flag BitHPI Status Port ID Flag Bit Done1 Flag Bit Reset1 Flag BitSPI Registers Mailbox Out Flag Bit Master Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable Bit SPI Control Register Byte Mode BitRead Enable Bit SCK Strobe Bit Transfer Interrupt Enable Bit SPI Interrupt Enable RegisterTransmit Interrupt Enable Bit Fifo Error Flag Bit SPI Interrupt Clear Register Receive Interrupt Flag BitTransmit Interrupt Flag Bit Transfer Interrupt Flag Bit CRC Clear Bit CRC Mode Definition CRCMode CRC Polynomial 1514CRC Enable Bit SPI CRC Value Register Receive CRC Bit SPI Transmit Address Register 0xC0D8 R/W SPI Data Register 0xC0D6 R/WSPI Data Register SPI Transmit Address Register SPI Transmit Count Register SPI Receive Address RegisterSPI Receive Count Register Uart Registers Receive buffer full Receive buffer empty Uart Status Register 0xC0E2 RUart Status Register Uart Data Register 0xC0E4 R/W PWM Registers Register Name Address PWM Enable BitPWM Registers PWM Control Register PWM 1 Enable Bit PWM 3 Enable BitPWM 2 Enable Bit PWM 0 Enable Bit PWM n Stop Register R/W PWM n Start Register R/WPWM n Start Register PWM n Stop Register PWM Cycle Count Register 0xC0FA R/W PWM Cycle Count Register Pin Diagram Pin DescriptionsPin Descriptions Name Type SCK SPI SCK D11/MOSIMosi SPI Mosi D8/MISO GPIO27/RX GPIO29/OTGIDGPIO28/TX GPIO26/CTS/PWM3 Booster Power input 2.7V to Tie to Gnd for normal operation Operating Conditions DC CharacteristicsAbsolute Maximum Ratings Crystal Requirements XTALIN, Xtalout USB Transceiver GND AC Timing Characteristics Reset TimingClock Timing Sram Read Cycle15 Sram Read Cycle Parameters Description Min Typical Max UnitLOW Parameter Description Min Typical Max Unit Sram Write CycleSram Write Cycle Parameters High I2C Eeprom Timing-Serial IO SCLSDA OUT HPI Host Port Interface Write Cycle Timing Read Pulse Width Chip Select Hold Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time HSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit IDE Timing Register Summary Hardware CTS/RTS HandshakeRegister Summary HSS SOF/EOP CRC SOF/EOP2 Ordering Information Ordering Code Package Type Package DiagramsOrdering Information Pb-Free Document History Orig. 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